Probablistically determining memory portions for select gate scanning

1 . A method comprising:

retrieving a read disturb scan counter;

determining that the read disturb scan counter satisfies a read disturb scan threshold;

probabilistically determining a read operation number using a read operation window size in response to determining that the read disturb scan counter satisfies the read disturb scan threshold, wherein the read operation number is less than or equal to the read operation window size;

receiving, by a memory subsystem, a read command from a host device;

determining a memory address using the read command;

determining that a read operation count for the read command corresponds to the read operation number;

flagging the memory address to have a select gate of the memory address scanned; and

scanning the select gate of the memory address in response to flagging the memory address.

2 . The method of claim 1 , further comprising:

receiving an erase operation from the host device;

determining the erase operation is directed to the flagged memory address; and

erasing the memory address in response to determining the memory address, wherein scanning the select gate of the memory address is further in response to erasing the memory address.

3 . The method of claim 1 , further comprising:

determining that the memory address failed the select gate scan; and

retiring the memory address in response to determining that the memory address failed the select gate scan.

4 . The method of claim 1 , further comprising:

determining that the memory address failed the select gate scan;

determining that a select gate touch-up count does not satisfy a touch-up threshold; and

performing a select gate touch-up in response to determining that the select gate touch-up count does not satisfy the touch-up threshold.

5 . The method of claim 4 , further comprising:

rescanning the select gate of the memory address in response to performing the select gate touch-up.

6 . The method of claim 1 , further comprising:

determining a read count for the memory subsystem; and

determining that the read count satisfies a read count threshold, wherein probabilistically determining the read operation number is further in response to the read count satisfying the read count threshold.

7 . The method of claim 6 , further comprising:

updating the read operation window size using the read count in response to the read count satisfying the read count threshold.

8 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

retrieve a read disturb scan counter;

determine that the read disturb scan counter satisfies a read disturb scan threshold;

probabilistically determine a read operation number using a read operation window size in response to determining that the read disturb scan counter satisfies the read disturb scan threshold, the read operation number is less than or equal to the read operation window size;

receive, by a memory subsystem, a read command from a host device;

determine a memory address using the read command;

determine that the read command corresponds to the read operation number;

flag the memory address to have a select gate of the memory address scanned; and

scan the select gate of the memory address in response to flagging the memory address.

9 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

receive an erase operation from the host device;

determine the erase operation is directed to the flagged memory address; and

erase the memory address in response to determining the memory address, wherein scanning the select gate of the memory address is further in response to erasing the memory address.

10 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

determine that the memory address failed the select gate scan; and

retire the memory address in response to determining that the memory address failed the select gate scan.

11 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

determine that the memory address failed the select gate scan;

determine that a select gate touch-up count does not satisfy a touch-up threshold; and

perform a select gate touch-up in response to determining that the select gate touch-up count does not satisfy the touch-up threshold.

12 . The non-transitory computer-readable storage medium of claim 11 , wherein the processing device is further to:

rescan the select gate of the memory address in response to performing the select gate touch-up.

13 . The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

determine a read count for the memory subsystem; and

determine that the read count satisfies a read count threshold, wherein probabilistically determining the read operation number is further in response to the read count satisfying the read count threshold.

14 . The non-transitory computer-readable storage medium of claim 13 , wherein the processing device is further to:

update the read operation window size using the read count in response to the read count satisfying the read count threshold.

15 . A system comprising:

a plurality of memory devices; and

a processing device, operatively coupled with the plurality of memory devices, to:

retrieve a read disturb scan counter;

determine that the read disturb scan counter satisfies a read disturb scan threshold;

probabilistically determine a read operation number using a read operation window size in response to determining that the read disturb scan counter satisfies the read disturb scan threshold, wherein the read operation number is less than or equal to the read operation window size;

receive, by a memory subsystem, a read command from a host device;

determine a memory address using the read command;

determine that a read operation count for the read command corresponds to the read operation number;

flag the memory address to have a select gate of the memory address scanned;

receive an erase operation from the host device;

determine the erase operation is directed to the flagged memory address; and

erase the memory address in response to determining the memory address; and

scan the select gate of the memory address in response to erasing the memory address.

16 . The system of claim 15 , wherein the processing device is further to:

determine that the memory address failed the select gate scan; and

retire the memory address in response to determining that the memory address failed the select gate scan.

17 . The system of claim 15 , wherein the processing device is further to:

determine that the memory address failed the select gate scan;

determine that a select gate touch-up count does not satisfy a touch-up threshold; and

perform a select gate touch-up in response to determining that the select gate touch-up count does not satisfy the touch-up threshold.

18 . The system of claim 17 , wherein the processing device is further to:

rescan the select gate of the memory address in response to performing the select gate touch-up.

19 . The system of claim 15 , wherein the processing device is further to:

determine a read count for the memory subsystem; and

determine that the read count satisfies a read count threshold, wherein probabilistically determining the read operation number is further in response to the read count satisfying the read count threshold.

20 . The system of claim 19 , wherein the processing device is further to:

update the read operation window size using the read count in response to the read count satisfying the read count threshold.