Memory system supporting multi-channel interface
A memory system includes a host and a memory device configured to transmit and receive data to and from the host through a plurality of channels. The host may include an error correction code (ECC) engine configured to generate ECC parity information corresponding to write data to be transmitted to the memory device, a data bus inversion (DBI) engine configured to generate DBI information corresponding to the write data to be transmitted to the memory device, and a memory controller configured to control the ECC engine and the DBI engine. The plurality of channels may include a data channel group, including a plurality of data channels, and an ECC channel group including a plurality of ECC channels. The DBI information may be transmitted from the host to the memory device through an unused ECC channel in the ECC channel group.
1 . A memory system comprising:
a host; and
a memory device configured to transmit and receive data to and from the host through a plurality of channels,
wherein,
the host comprises:
an error correction code (ECC) engine configured to generate ECC parity information corresponding to write data to be transmitted to the memory device;
a data bus inversion (DBI) engine configured to generate DBI information corresponding to the write data to be transmitted to the memory device; and
a memory controller configured to control the ECC engine and the DBI engine,
the plurality of channels comprise:
a data channel group comprising a plurality of data channels; and
an ECC channel group comprising a plurality of ECC channels, and
the DBI information is transmitted from the host to the memory device through an ECC channel in the ECC channel group that is currently unused for transmitting the ECC parity information based on an ECC algorithm.
2 . The memory system of claim 1 , wherein
the memory device comprises a plurality of memory dies,
the host is implemented as a logic die stacked vertically on a substrate, and
the plurality of memory dies are stacked vertically on the logic die.
3 . The memory system of claim 1 , wherein:
the host comprises an input/output (I/O) circuit configured to transmit a data corresponding to the write data, the ECC parity information, and the DBI information to the memory device through the plurality of channels, and
the DBI engine is configured to perform a DBI encoding operation on the write data based on a data pattern in the I/O circuit.
4 . The memory system of claim 3 , wherein the DBI engine is configured to perform a DBI encoding operation on the write data based on a result of comparing bits of the first data previously transmitted by the I/O circuit and bits of the write data, and to output the main data and the DBI information.
5 . The memory system of claim 4 , wherein the DBI engine is configured to flip the write data when the bits of the first data and the bits of the write data in the I/O circuit are the same for more than half of the bits of the first data.
6 . The memory system of claim 3 , wherein the ECC engine is configured to output the ECC parity information after performing an ECC encoding operation on the main data.
7 . The memory system of claim 3 , wherein the ECC engine is configured to output the ECC parity information after performing an ECC encoding operation on the main data and the DBI information.
8 . The memory system of claim 1 , wherein:
the ECC engine is configured to receive main data corresponding to read data and ECC parity information corresponding to the read data from the memory device and generate corrected main data by performing an ECC decoding operation on the main data based on the ECC parity information, and
the DBI engine is configured to receive DBI information corresponding to the read data from the memory device, receive the corrected main data from the ECC engine, and perform a DBI decoding operation on the corrected main data based on the DBI information.
9 . The memory system of claim 1 , wherein:
the host comprises an input/output (I/O) circuit configured to transmit a first data corresponding to the write data, the ECC parity information, and the DBI information to the memory device through the plurality of channels,
the memory device comprises:
a memory cell array comprising a plurality of banks; and
a local memory controller configured to control the memory cell array, and
the DBI engine is configured to perform a DBI encoding operation on the write data based on a data pattern in the local memory controller.
10 . The memory system of claim 9 , wherein:
the first data comprises a plurality of sub-data respectively corresponding to the plurality of banks, each sub-data of the plurality of sub-data having a portion of bits of the first data, and
the DBI engine is configured to perform a DBI encoding operation on the write data based on a result of comparing bits of a first sub-data of the plurality of sub-data transmitted to a selected bank corresponding to the first sub-data, among the plurality of banks, and first bits to be transmitted to the selected bank, among bits of the write data.
11 . The memory system of claim 10 , wherein the DBI engine is configured to flip the bits of the write data corresponding to the selected bank when the bits of the first sub-data of the plurality of sub-data corresponding to the selected bank and the bits of the write data corresponding to the selected bank are the same for more than half of the bits of the first sub-data of the plurality of sub-data.
12 . The memory system of claim 1 , wherein:
the memory device comprises a plurality of memory dies, and
each of the plurality of memory dies comprises:
a memory cell array;
a local memory controller configured to control the memory cell array; and
a read data bus inversion (RDBI) encoder configured to generate first main data and RDBI information by performing a DBI encoding operation on second main data stored in the each of the plurality of memory dies corresponding to a read request from the host.
13 . The memory system of claim 12 , wherein the host further comprises an RDBI decoder configured to receive the RDBI information, generated by the RDBI encoder, and first main data and perform a DBI decoding operation on the first main data based on the RDBI information.
14 . The memory system of claim 13 , wherein the RDBI encoder and the RDBI decoder are configured to transmit and receive data through an RDBI channel, different from channels of the ECC channel group.
15 . The memory system of claim 12 , wherein the RDBI encoder is configured to perform a DBI encoding operation on the second main data based on a data pattern of the local memory controller during a read operation.
16 . The memory system of claim 1 , wherein the ECC channel that is currently unused for transmitting the ECC parity information is a redundant ECC channel.
17 . A memory system comprising:
a logic die;
a plurality of memory dies stacked on the logic die; and
a plurality of channels configured to provide a signal transmission path between the logic die and the plurality of memory dies,
wherein,
the plurality of channels comprise:
a plurality of data channels configured to transmit and receive data; and
a plurality of error correction code (ECC) channels configured to transmit and receive ECC parity information, and
an ECC channel among the plurality of ECC channels, currently unused for transmitting the ECC parity information, is used to transmit and receive data bus inversion (DBI) information based on an ECC algorithm.
18 . The memory system of claim 17 , wherein
the logic die comprises:
an ECC engine configured to generate ECC parity information corresponding to write data to be transmitted to a selected memory die among the plurality of memory dies;
a DBI engine configured to generate DBI information corresponding to the write data;
a memory controller configured to control the ECC engine and the DBI engine; and
an input/output (I/O) circuit configured to transmit main data corresponding to the write data, the ECC parity information, and the DBI information to the plurality of memory dies through the plurality of channels, and
the DBI engine is configured to perform a DBI encoding operation on the write data based on a data pattern in the I/O circuit.
19 . The memory system of claim 17 , wherein
the logic die comprises:
an ECC engine configured to generate ECC parity information corresponding to write data to be transmitted to a selected memory die among the plurality of memory dies;
a DBI engine configured to generate DBI information corresponding to the write data; and
a memory controller configured to control the ECC engine and the DBI engine,
each of the plurality of memory dies comprises:
a memory cell array comprising a plurality of banks; and
a local memory controller configured to control the memory cell array, and
the DBI engine is configured to perform a DBI encoding operation on the write data based on a data pattern in the local memory controller.
20 . A memory system comprising:
a logic chip; and
a high-bandwidth memory configured to transmit and receive data to and from the logic chip through a plurality of channels and stacked on the logic chip in a vertical direction,
wherein,
the plurality of channels comprise:
a data channel group comprising a plurality of data channels; and
an error correction code (ECC) channel group comprising a plurality of ECC channels, and
data bus inversion (DBI) information is transmitted from the logic chip to the high-bandwidth memory through an ECC channel in the ECC channel group, currently unused for transmitting ECC parity information based on an ECC algorithm.