Non-contiguous data transfer techniques with multiple digital interfaces

1 . A method comprising:

receiving, by a data transfer controller connected to a first digital interface of a computer system, an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface;

reading, via a plurality of gather transactions on a second digital interface, the plurality of non-contiguous data elements from the memory of the computer system, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, wherein the second digital interface allows for use of a subset of overhead data of the first digital interface for the plurality of gather transactions, and wherein the subset of overhead data of the first digital interface for the plurality of gather transactions comprises at least one of: source/destination addresses, packet headers, cyclic redundancy check (CRC) values, parity bits, timestamps, version numbers, or data types;

writing the plurality of non-contiguous data elements into a contiguous data block in a buffer; and

providing, to the peripheral device via the first digital interface, an indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface.

2 . The method of claim 1 , wherein:

the first digital interface corresponds to a control plane of the data transfer controller and the second digital interface corresponds to a data plane of the data transfer controller;

the first digital interface corresponds to a control plane and a data plane of the peripheral device; and

the second digital interface corresponds to a control plane and a data plane of the memory of the computer system.

3 . The method of claim 2 , wherein:

a PCIe interface comprises a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer;

the first digital interface is a modified Peripheral Component Interconnect Express (PCIe) interface; and

one of the PCIe physical layer or the PCIe data link layer is absent or modified in the modified PCIe interface.

4 . The method of claim 1 , wherein:

the received instruction comprises a plurality of non-contiguous virtual memory addresses each addressable by a processor of the computer system, the data transfer controller, and the peripheral device; and

each address of the plurality of non-contiguous virtual memory addresses is associated with a respective data element of the plurality of non-contiguous data elements.

5 . The method of claim 1 , wherein the buffer is one of:

the memory of the computer system, wherein writing the plurality of non-contiguous data elements into the contiguous data block comprises initiating one or more write transactions on the second digital interface; or

a cache of the data transfer controller.

6 . The method of claim 1 , wherein providing the indication that the contiguous data block is available for transfer comprises one of: releasing a semaphore, setting a flag, or triggering an interrupt.

7 . The method of claim 1 , wherein the peripheral device is a network interface controller (NIC).

8 . A method comprising:

receiving, by a data transfer controller connected to a first digital interface of a computer system, an instruction to distribute a plurality of data elements of a contiguous data block to a plurality of non-contiguous addresses in a memory of the computer system, wherein the contiguous data block is associated with a peripheral device connected to the first digital interface;

receiving, from the peripheral device via the first digital interface, an indication that a write transaction using the first digital interface is complete, wherein the write transaction corresponds to a transfer of the contiguous data block from the peripheral device to a buffer;

reading the plurality of data elements from the contiguous data block in the buffer; and

writing, via a plurality of scatter transactions on a second digital interface, the plurality of data elements to the plurality of non-contiguous addresses in the memory of the computer system, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, wherein the second digital interface allows for use of a subset of overhead data of the first digital interface for the plurality of scatter transactions, and wherein the subset of overhead data of the first digital interface for the plurality of scatter transactions comprises at least one of: source/destination addresses, packet headers, cyclic redundancy check (CRC) values, parity bits, timestamps, version numbers, or data types.

9 . The method of claim 8 , wherein:

the first digital interface corresponds to a control plane of the data transfer controller and the second digital interface corresponds to a data plane of the data transfer controller;

the first digital interface corresponds to a control plane and a data plane of the peripheral device; and

the second digital interface corresponds to a control plane and a data plane of the memory of the computer system.

10 . The method of claim 9 , wherein:

a PCIe interface comprises a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer;

The first digital interface is a modified Peripheral Component Interconnect Express (PCIe) interface; and

one of the PCIe physical layer or the PCIe data link layer is absent or modified in the modified PCIe interface.

11 . The method of claim 8 , wherein each address of the plurality of non-contiguous addresses is a virtual memory address addressable by a processor of the computer system, the data transfer controller, and the peripheral device.

12 . The method of claim 8 , wherein the buffer is one of:

the memory of the computer system, wherein reading the plurality of data elements from the contiguous data block comprises initiating one or more read transactions on the second digital interface; or

a cache of the data transfer controller.

13 . The method of claim 8 , wherein receiving the indication that the write transaction is complete comprises one of: obtaining a semaphore, reading a flag, or receiving an interrupt.

14 . The method of claim 8 , wherein the peripheral device is a network interface controller (NIC).

15 . A method comprising:

receiving, by a data transfer controller connected to a first digital interface of a computer system, an instruction to transfer a plurality of non-contiguous data elements from a first process memory space in a memory of the computer system to a plurality of respective non-contiguous addresses in a second process memory space in the memory of the computer system;

reading, via a plurality of gather transactions on a second digital interface, the plurality of non-contiguous data elements from the first process memory space, wherein the second digital interface is connected to the data transfer controller and the memory of the computer system, wherein the second digital interface allows for use of a subset of overhead data of the first digital interface for the plurality of gather transactions, and wherein the subset of overhead data of the first digital interface for the plurality of gather transactions comprises at least one of: source/destination addresses, packet headers, cyclic redundancy check (CRC) values, parity bits, timestamps, version numbers, or data types; and

writing, via a plurality of scatter transactions on the second digital interface, the plurality of non-contiguous data elements to the plurality of respective non-contiguous addresses in the second process memory space.

16 . The method of claim 15 , wherein:

the first digital interface corresponds to a control plane of the data transfer controller and the second digital interface corresponds to a data plane of the data transfer controller; and

the second digital interface corresponds to a control plane and a data plane of the memory of the computer system.

17 . The method of claim 16 , wherein a peripheral device is connected to the first digital interface, and wherein a data transaction of the peripheral device uses the first digital interface.

18 . The method of claim 16 , wherein:

a PCIe interface comprises a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer;

the first digital interface is a modified Peripheral Component Interconnect Express (PCIe) interface; and

one of the PCIe physical layer or the PCIe data link layer is absent or modified in the modified PCIe interface.

19 . The method of claim 15 , wherein each address of the plurality of respective non-contiguous addresses is a virtual memory address addressable by a processor of the computer system, the data transfer controller, and a peripheral device.

20 . The method of claim 19 , wherein the peripheral device is a network interface controller (NIC).

21 . A system for high-speed network communication in a data center, the system comprising:

one or more processing units;

a memory coupled to the one or more processing units;

a network interface coupled to the one or more processing units and the memory; and

a data transfer controller coupled to the one or more processing units, the memory, and the network interface, wherein the data transfer controller is to perform operations comprising:

receiving, from the one or more processing units via a first digital interface, an instruction to prepare a plurality of non-contiguous data elements in the memory for transfer to the network interface, wherein the network interface is connected to the first digital interface;

reading, via a plurality of gather transactions on a second digital interface, the plurality of non-contiguous data elements from the memory, wherein the second digital interface is connected to the data transfer controller and the memory, and wherein the second digital interface allows for use of a subset of overhead data of the first digital interface for the plurality of gather transactions, and wherein the subset of overhead data of the first digital interface for the plurality of gather transactions comprises at least one of: source/destination addresses, packet headers, cyclic redundancy check (CRC) values, parity bits, timestamps, version numbers, or data types;

writing the plurality of non-contiguous data elements into a contiguous data block in a buffer; and

providing, to the network interface via the first digital interface, an indication that the contiguous data block is available for transfer from the buffer to the network interface via the first digital interface.

22 . The system of claim 21 , wherein:

the first digital interface corresponds to a control plane of the data transfer controller and the second digital interface corresponds to a data plane of the data transfer controller;

the first digital interface corresponds to a control plane and a data plane of the network interface; and

the second digital interface corresponds to a control plane and a data plane of the memory.

23 . The system of claim 22 , wherein:

a PCIe interface comprises a PCIe physical layer, a PCIe data link layer, and a PCIe transaction layer;

the first digital interface is a modified Peripheral Component Interconnect Express (PCIe) interface; and

one of the PCIe physical layer or the PCIe data link layer is absent or modified in the modified PCIe interface.

24 . The system of claim 21 , wherein:

the received instruction comprises a plurality of non-contiguous virtual memory addresses each addressable by the one or more processing units, the data transfer controller, and the network interface; and

each address of the plurality of non-contiguous virtual memory addresses is associated with a respective data element of the plurality of non-contiguous data elements.

25 . The system of claim 21 , wherein the buffer is one of:

the memory, wherein writing the plurality of non-contiguous data elements into the contiguous data block comprises initiating one or more write transactions on the second digital interface; or

a cache of the data transfer controller.

26 . The system of claim 21 , wherein providing the indication that the contiguous data block is available for transfer comprises one of: releasing a semaphore, setting a flag, or triggering an interrupt.