IP Library › Granted Patent US 12688124
Granted Patent B2
US 12688124 · App. 18/674,590 · Granted Jul 21, 2026

Cached random access memory (RAM) counter system

Inventors: Tama Gal (Haifa, IL); Yevgeny Yankilevich (Tirat Carmel, IL); Gil Savir (Haifa, IL)
Assignee: Microsoft Technology Licensing, LLC
G06F12/0802
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Quick Facts
Patent No.
US 12688124
App. No.
18/674,590
Granted
Jul 21, 2026
Kind
B2
Abstract

A cached random access memory (RAM) counter system comprises a plurality of incremental counter circuits associated with a plurality of count values that each maintain a plurality of least-significant bits of a respective count value and a respective carry bit; a RAM circuit that stores a plurality of most-significant bits of each respective count value; a single-bit multiplexer that receives the respective carry bit from each of the plurality of counter circuits and selectively provides a carry bit output for the respective count value; and an adder circuit that adds the carry bit output for the respective count value from the single-bit multiplexer to the plurality of most-significant bits of the respective count value and provides an updated plurality of most-significant bits of the respective count value for storage in the RAM circuit.

Claims (43)

1 . A cached random-access memory (RAM) counter system comprising:

a plurality of incremental counter circuits associated with a plurality of count values that each maintain a plurality of least-significant bits of a respective count value and a respective carry bit;

a RAM circuit that stores a plurality of most-significant bits of each respective count value;

a single-bit multiplexer that receives the respective carry bit from each of the plurality of incremental counter circuits and selectively provides a carry bit output for the respective count value;

an adder circuit that adds the carry bit output for the respective count value from the single-bit multiplexer to the plurality of most-significant bits of the respective count value and provides an updated plurality of most-significant bits of the respective count value for storage in the RAM circuit; and

a count value read circuit that receives a read address associated with the respective count value and provides the read address to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

2 . The cached RAM counter system of claim 1 , further comprising:

a multi-bit multiplexer that receives the plurality of least-significant bits of each of the plurality of count values and selectively provides an up-to-date respective plurality of least-significant bits of the respective count value in response to receiving a read address associated with the respective count value.

3 . The cached RAM counter system of claim 2 , wherein the count value read circuit further provides the read address to the multi-bit multiplexer to select the up-to-date respective plurality of least-significant bits of the respective count value.

4 . The cached RAM counter system of claim 3 , wherein the count value read circuit comprises a free-running counter that sequences through the plurality of count values and provides the read address associated with each count value to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

5 . The cached RAM counter system of claim 3 , wherein the count value read circuit concatenates the updated plurality of most-significant bits of the respective count value with the up-to-date respective plurality of least-significant bits to generate an up-to-date respective count value.

6 . The cached RAM counter system of claim 1 , further comprising:

a one-hot shift register signal circuit that generates a one-hot signal that resets the respective carry bit for each of the plurality of incremental counter circuits.

7 . The cached RAM counter system of claim 1 , further comprising:

a plurality of shift registers that reset the respective carry bit for each of the plurality of incremental counter circuits.

8 . A multi-bit linear feedback shift register (LFSR) counter system comprising:

a plurality of incremental counter circuits associated with a plurality of count values that each maintain a plurality of least-significant bits of a respective count value and a respective carry bit;

a RAM circuit that stores a plurality of most-significant bits of each respective count value;

a single-bit multiplexer that receives the respective carry bit from each of the plurality of incremental counter circuits and selectively provides a carry bit output for the respective count value;

an adder circuit that adds the carry bit output for the respective count value from the single-bit multiplexer to the plurality of most-significant bits of the respective count value and provides an updated plurality of most-significant bits of the respective count value for storage in the RAM circuit, wherein the respective count value is formed from a combination of the updated plurality of most-significant bits of the respective count value with the plurality of least-significant bits of the respective count value; and

a count value read circuit that receives a read address associated with the respective count value and provides the read address to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

9 . The multi-bit LFSR counter system of claim 8 , further comprising:

a multi-bit multiplexer that receives the plurality of least-significant bits of each of the plurality of count values and selectively provides an up-to-date respective plurality of least-significant bits of the respective count value in response to receiving the read address associated with the respective count value.

10 . The multi-bit LFSR counter system of claim 9 , wherein the count value read circuit further provides the read address to the multi-bit multiplexer to select the up-to-date respective plurality of least-significant bits of the respective count value.

11 . The multi-bit LFSR counter system of claim 10 , wherein the count value read circuit further sequences through the plurality of count values and provides the read address associated with each count value to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

12 . The multi-bit LFSR counter system of claim 10 , wherein the count value read circuit concatenates the updated plurality of most-significant bits of the respective count value with the up-to-date respective plurality of least-significant bits to generate an up-to-date respective count value.

13 . The multi-bit LFSR counter system of claim 8 , further comprising:

a plurality of shift registers that reset the respective carry bit for each of the plurality of incremental counter circuits.

14 . An apparatus comprising:

a plurality of incremental counter circuits associated with a plurality of count values that each maintain a plurality of least-significant bits of a respective count value and a respective carry bit;

a RAM circuit that stores a plurality of most-significant bits of each respective count value;

a single-bit multiplexer that receives the respective carry bit from each of the plurality of incremental counter circuits and selectively provides a carry bit output for the respective count value;

an adder circuit that adds the carry bit output for the respective count value from the single-bit multiplexer to the plurality of most-significant bits of the respective count value and provides an updated plurality of most-significant bits of the respective count value for storage in the RAM circuit; and

a count value read circuit that receives a read address associated with the respective count value and provides the read address to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

15 . The apparatus of claim 14 , further comprising:

a multi-bit multiplexer that receives the plurality of least-significant bits of each of the plurality of count values and selectively provides an up-to-date respective plurality of least-significant bits of the respective count value in response to receiving the read address associated with the respective count value.

16 . The apparatus of claim 15 , wherein the count value read circuit further provides the read address to the multi-bit multiplexer to select the up-to-date respective plurality of least-significant bits of the respective count value.

17 . The apparatus of claim 16 , wherein the count value read circuit comprises a free-running counter that sequences through the plurality of count values and provides the read address associated with each count value to: the single-bit multiplexer to select the carry bit output for the respective count value and the RAM circuit to obtain the plurality of most-significant bits of the respective count value for the respective count value stored in the RAM circuit.

18 . The apparatus of claim 16 , wherein the count value read circuit concatenates the updated plurality of most-significant bits of the respective count value with the up-to-date respective plurality of least-significant bits to generate an up-to-date respective count value.

19 . The apparatus of claim 14 , further comprising:

a one-hot shift register signal circuit that generates a one-hot signal that resets the respective carry bit for each of the plurality of incremental counter circuits.

20 . The apparatus of claim 14 , further comprising:

a plurality of shift registers that reset the respective carry bit for each of the plurality of incremental counter circuits.