Multi-stack compute chip and memory architecture
Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.
1 . An apparatus comprising:
a package including:
a plurality of computing stacks integrated within the package, wherein a first computing stack and a second computing stack of the plurality of computing stacks each include at least one compute chip and memory, wherein the at least one compute chip is configured to access data in the memory of at least one of the first computing stack or the second computing stack to execute instructions of a program; and
one or more interconnects of the package that couple the first computing stack to at least the second computing stack for sharing the memory.
2 . The apparatus of claim 1 , wherein the memory is one or more memory die.
3 . The apparatus of claim 1 , wherein the memory of the first computing stack includes dynamic random-access memory (DRAM) and the memory of the second computing stack includes non-volatile memory.
4 . The apparatus of claim 1 , wherein the memory of the first computing stack includes dynamic random-access memory (DRAM) and non-volatile memory.
5 . The apparatus of claim 1 , wherein the memory of the first computing stack includes a first portion and a second portion, wherein the first portion is embedded in the at least one compute chip, and wherein the second portion is separate from and communicably coupled to the at least one compute chip.
6 . The apparatus of claim 1 , wherein the first computing stack further includes one or more memory request units adapted to perform at least one of:
send and receive data over the one or more interconnects between the memory of the first computing stack and the second computing stack;
provide coherent shared memory across memory of the plurality of computing stacks; or
provide coherent shared memory across memory of a subset of the plurality of computing stacks.
7 . The apparatus of claim 1 , wherein the at least one compute chip of the first computing stack is configured to access data from the memory of the first computing stack faster than data from the memory of the second computing stack, wherein the at least one compute chip of the first computing stack accesses the data from the memory of the second computing stack over the one or more interconnects.
8 . The apparatus of claim 1 , wherein the one or more interconnects are disposed on or within at least one of a silicon interposer, a silicon bridge, a glass interposer, an organic package, or a silicon photonic interconnect.
9 . The apparatus of claim 1 , wherein the plurality of computing stacks are interconnected with the one or more interconnects in an array topology.
10 . The apparatus of claim 1 , wherein the plurality of computing stacks are interconnected with the one or more interconnects in a grid topology.
11 . The apparatus of claim 1 , wherein the apparatus is communicably coupled to at least one additional package which includes a plurality of computing stacks.
12 . The apparatus of claim 1 , wherein the memory of the first computing stack is disposed in a stacked arrangement above or below the at least one compute chip of the first computing stack, and the stacked arrangement is disposed on a substrate of the apparatus.
13 . The apparatus of claim 1 , wherein the memory of the first computing stack is disposed in a side-by-side arrangement with the at least one compute chip of the first computing stack.
14 . The apparatus of claim 13 , wherein the side-by-side arrangement is disposed on a substrate of the apparatus.
15 . The apparatus of claim 13 , wherein the side-by-side arrangement is disposed in a stacked arrangement above or below a circuitry die of the first computing stack, and the stacked arrangement is disposed on a substrate of the apparatus.
16 . The apparatus of claim 15 , wherein the circuitry die includes at least one of:
a memory controller;
cache;
data fabric;
network on a chip (NoC); or
memory interface circuits.
17 . A system on package (SoP) comprising:
a plurality of computing stacks integral with a substrate of a package, wherein:
each computing stack of the plurality of computing stacks includes at least one compute chip coupled to one or more memory dies; and
at least a first computing stack of the plurality of computing stacks is coupled to at least a second computing stack and a third computing stack of the plurality of computing stacks via interconnects for sharing the one or more memory dies, wherein the at least one compute chip is configured to access data in the one or more memory dies of at least one of the first computing stack or the second computing stack to execute instructions of a program; and
one or more interfaces of the package to couple the package to at least one external device.
18 . The system on package (SoP) of claim 17 , wherein the at least one external device includes at least one of:
an integrated circuit;
external memory;
a motherboard; or
an additional package.
19 . A method for fabricating a multi-stack package comprising:
forming a plurality of computing stacks, wherein a first computing stack and a second computing stack of the plurality of computing stacks each include at least one compute chip and memory, wherein the at least one compute chip is configured to access data in the memory of at least one of the first computing stack or the second computing stack to execute instructions of a program; and
disposing the plurality of computing stacks on a substrate of a package, the first computing stack and the second computing stack being electrically connected on the substrate via one or more interconnects for sharing the memory.
20 . The apparatus of claim 1 , wherein the plurality of computing stacks is integral with a substrate of the package.
21 . The system on package (SoP) of claim 17 , wherein the one or more memory dies of the first computing stack include dynamic random-access memory (DRAM) and the one or more memory dies of the second computing stack include non-volatile memory.
22 . The system on package (SoP) of claim 17 , wherein the one or more memory dies of the first computing stack include dynamic random-access memory (DRAM) and non-volatile memory.
23 . The system on package (SoP) of claim 17 , wherein the first computing stack includes embedded memory in the at least one compute chip.
24 . The system on package (SoP) of claim 17 , wherein the first computing stack includes one or more memory request units adapted to perform at least one of:
send and receive data over the interconnects between the one or more memory dies of the first computing stack and the one or more memory dies of the second computing stack;
provide coherent shared memory across the one or more memory dies of the plurality of computing stacks; or
provide coherent shared memory across the one or more memory dies of a subset of the plurality of computing stacks.
25 . The system on package (SoP) of claim 17 , wherein the at least one compute chip of the first computing stack is configured to access data from the one or more memory dies of the first computing stack faster than data from the one or more memory dies of the second computing stack, wherein the at least one compute chip of the first computing stack accesses the data from the one or more memory dies of the second computing stack over the interconnects.
26 . The system on package (SoP) of claim 17 , wherein the plurality of computing stacks are interconnected with the interconnects in an array topology.
27 . The system on package (SoP) of claim 17 , wherein the plurality of computing stacks are interconnected with the interconnects in a grid topology.
28 . The system on package (SoP) of claim 17 , wherein the one or more memory dies of the first computing stack are disposed in a stacked arrangement above or below the at least one compute chip of the first computing stack, and the stacked arrangement is disposed on the substrate of the package.
29 . The system on package (SoP) of claim 17 , wherein the one or more memory dies of the first computing stack are disposed in a side-by-side arrangement with the at least one compute chip of the first computing stack.
30 . The system on package (SoP) of claim 29 , wherein the side-by-side arrangement is disposed on the substrate of the package.
31 . The system on package (SoP) of claim 29 , wherein the side-by-side arrangement is disposed in a stacked arrangement above or below a circuitry die of the first computing stack, and the stacked arrangement is disposed on the substrate of the package.
32 . The system on package (SoP) of claim 31 , wherein the circuitry die includes at least one of:
a memory controller;
cache;
data fabric;
network on a chip (NoC); or
memory interface circuits.
33 . The method of claim 19 , wherein the memory is one or more memory dies.
34 . The method of claim 19 , wherein the memory of the first computing stack is formed to include dynamic random-access memory (DRAM) and the memory of the second computing stack is formed to include non-volatile memory.
35 . The method of claim 19 , wherein the memory of the first computing stack is formed to include dynamic random-access memory (DRAM) and non-volatile memory.
36 . The method of claim 19 , wherein the memory of the first computing stack is formed to include a first portion and a second portion, wherein the first portion is embedded in the at least one compute chip, and wherein the second portion is separate from and communicably coupled to the at least one compute chip.
37 . The method of claim 19 , wherein the first computing stack is formed to include one or more memory request units adapted to perform at least one of
send and receive data over the one or more interconnects between the memory of the first computing stack and the second computing stack;
provide coherent shared memory across memory of the plurality of computing stacks; or
provide coherent shared memory across memory of a subset of the plurality of computing stacks.
38 . The method of claim 19 , wherein the at least one compute chip of the first computing stack is configured to access data from the memory of the first computing stack faster than data from the memory of the second computing stack, wherein the at least one compute chip of the first computing stack accesses the data from the memory of the second computing stack over the one or more interconnects.
39 . The method of claim 19 , further comprising disposing the one or more interconnects on or within at least one of a silicon interposer, a silicon bridge, a glass interposer, an organic package, or a silicon photonic interconnect.
40 . The method of claim 19 , further comprising coupling the plurality of computing stacks with the one or more interconnects in an array topology.
41 . The method of claim 19 , further comprising coupling the plurality of computing stacks with the one or more interconnects in a grid topology.
42 . The method of claim 19 , further comprising disposing the memory of the first computing stack in a stacked arrangement above or below the at least one compute chip of the first computing stack, and disposing the stacked arrangement on a substrate of the multi-stack package.
43 . The method of claim 19 , further comprising disposing the memory of the first computing stack in a side-by-side arrangement with the at least one compute chip of the first computing stack.
44 . The method of claim 43 , further comprising disposing the side-by-side arrangement on a substrate of the multi-stack package.
45 . The method of claim 43 , further comprising disposing the side-by-side arrangement in a stacked arrangement above or below a circuitry die of the first computing stack, and disposing the stacked arrangement on a substrate of the multi-stack package.
46 . The method of claim 45 , wherein the circuitry die includes at least one of:
a memory controller;
cache;
data fabric;
network on a chip (NoC); or
memory interface circuits.