Dual-phase interfaces on a shared bus

1 . An information handling system comprising:

at least one processor;

an interface configured to communicatively couple the at least one processor to an information handling resource via a first communications protocol; and

an interface controller configured to manage the interface;

wherein the interface controller is configured to:

transmit a payload to the information handling resource via one or more signal lines of the interface, wherein the payload is transmitted via a second communications protocol different from the first communications protocol, and wherein the payload includes information usable to establish communications via the first communications protocol, the information including a version number associated with the first communications protocol, a bit rate associated with the first communications protocol, and one or more mode settings associated with the first communications protocol; and

in response to the payload being received by the information handling resource, establish communications via the first communications protocol with the information handling resource over the one or more signal lines of the interface.

2 . The information handling system of claim 1 , wherein the first communications protocol is serial general purpose input/output (SGPIO).

3 . The information handling system of claim 1 , wherein the second communications protocol is universal asynchronous receiver/transmitter (UART).

4 . The information handling system of claim 1 , wherein the interface controller comprises a field-programmable gate array (FPGA).

5 . The information handling system of claim 1 , wherein the information handling system is a baseboard management controller (BMC).

6 . The information handling system of claim 1 , wherein the interface includes a plurality of signal lines, and wherein only a single one of the plurality of signal lines is used to transmit the payload.

7 . A method comprising:

transmitting, by an interface controller of an interface that is configured to communicatively couple to an information handling resource via a first communications protocol, a payload from an information handling system to the information handling resource via one or more signal lines of the interface and via a second communications protocol different from the first communications protocol, wherein the payload includes information usable to establish communications via the first communications protocol, the information including a version number associated with the first communications protocol, a bit rate associated with the first communications protocol, and one or more mode settings associated with the first communications protocol; and

in response to the payload being received by the information handling resource, the interface controller establishing communications via the first communications protocol with the information handling resource over the one or more signal lines of the interface.

8 . The method of claim 7 , wherein the first communications protocol is serial general purpose input/output (SGPIO).

9 . The method of claim 7 , wherein the second communications protocol is universal asynchronous receiver/transmitter (UART).

10 . The method of claim 7 , wherein the interface controller comprises a field-programmable gate array (FPGA).

11 . The method of claim 7 , wherein the information handling system is a baseboard management controller (BMC).

12 . The method of claim 7 , wherein the interface includes a plurality of signal lines, and wherein only a single one of the plurality of signal lines is used to transmit the payload.

13 . An article of manufacture comprising a non-transitory, computer-readable medium having computer-executable instructions thereon that are executable by a processor of an interface controller of an interface that is configured to communicatively couple to an information handling resource via a first communications protocol for:

transmitting a payload from an information handling system to the information handling resource via one or more signal lines of the interface and via a second communications protocol different from the first communications protocol, wherein the payload includes information usable to establish communications via the first communications protocol, the information including a version number associated with the first communications protocol, a bit rate associated with the first communications protocol, and one or more mode settings associated with the first communications protocol; and

in response to the payload being received by the information handling resource, the interface controller establishing communications via the first communications protocol with the information handling resource over the one or more signal lines of the interface.

14 . The article of claim 13 , wherein the first communications protocol is serial general purpose input/output (SGPIO).

15 . The article of claim 13 , wherein the second communications protocol is universal asynchronous receiver/transmitter (UART).

16 . The article of claim 13 , wherein the interface controller comprises a field-programmable gate array (FPGA).

17 . The article of claim 13 , wherein the information handling system is a baseboard management controller (BMC).

18 . The article of claim 13 , wherein the interface includes a plurality of signal lines, and wherein only a single one of the plurality of signal lines is used to transmit the payload.