Neural processor

1 . A processor comprising:

a plurality of neural cores, each of which comprises a plurality of controllable ports;

at least one forward data line configured for one-way transmission of data in a forward direction between the plurality of neural cores; and

at least one backward data line configured for one-way transmission of data in a backward direction between the plurality of neural cores,

wherein a data path for the plurality of neural cores is determined among a plurality of candidate data paths according to a type of computation performed by the at least one of the plurality of neural cores,

the determined data path is configured on the at least one forward data line and the at least one backward data line by controlling controllable ports of the plurality of neural cores, and

the controlling controllable ports comprises turning on or off at least one controllable port of the controllable ports of the plurality of neural cores,

wherein controlling the controllable ports further comprises:

in association with determining the determined data path, turning on at least one controllable port corresponding to the determined data path and turning off at least one controllable port corresponding to a non-selected data path among the plurality of candidate data paths.

2 . The processor of claim 1 , wherein the plurality of neural cores is operably coupled in series via the at least one forward data line and the at least one backward data line.

3 . The processor of claim 1 , wherein the plurality of neural cores comprises a first neural core and a second neural core,

wherein a forward data path is configured by turning on a controllable port on the at least one forward data line between the first neural core and the second neural core and data is transmitted via the forward data path from the first neural core to the second neural core.

4 . The processor of claim 3 , wherein a backward data path is configured by turning on a controllable port on the at least one backward data line between the first neural core and the second neural core, and data is transmitted via the backward data path from the second neural core to the first neural core.

5 . The processor of claim 1 , further comprising a first memory operably coupled to the plurality of neural cores,

wherein the plurality of neural cores comprises a first neural core and a second neural core,

wherein the determined data path comprises a first and second forward sub-paths configured on the at least one forward data line and a first and second backward sub-paths configured on the at least one backward data line, and

wherein the first forward sub-path is from the first memory to the first neural core,

the second forward sub-path is from the first neural core to the second neural core,

the first backward sub-path is from the second neural core to the first neural core, and

the second backward sub-path is from the first neural core to the first memory.

6 . The processor of claim 5 , wherein the determined data path further comprises a third forward sub-path configured on the at least one forward data line and a third backward sub-path configured on the at least one backward data line,

the third forward sub-path is from the second neural core to a second memory, and

the third backward sub-path is from the second memory to the second neural core, and

wherein the second memory is the same as or different from the first memory.

7 . The processor of claim 1 , further comprising a first memory operably coupled to the plurality of neural cores,

wherein the plurality of neural cores comprises a first neural core and a second neural core,

wherein a first data path is configured by controlling controllable ports of the plurality of neural cores, the first data path comprises a forward sub-path configured on the at least one forward data line and a backward sub-path configured on the at least one backward data line, the forward sub-path of the first data path is from the first memory to the first neural core, and the backward sub-path of the first data path is from the first neural core to the first memory,

wherein a second data path is configured by controlling controllable ports of the plurality of neural cores, the second data path comprises a forward sub-path configured on the at least one forward data line and a backward sub-path configured on the at least one backward data line, the backward sub-path of the second data path is from a second memory to the second neural core, and the forward sub-path of the second data path is from the second neural core to the second memory, and

wherein the second memory is the same as or different from the first memory.

8 . The processor of claim 1 , wherein the plurality of neural cores comprises a first neural core and a second neural core,

wherein the determined data path comprises first and second forward sub-paths configured on the at least one forward data line, the first forward sub-path is from the first memory to the first neural core, and the second forward sub-path is from the first neural core to a second memory, and

wherein the second memory is the same as or different from the first memory.

9 . The processor of claim 1 , wherein the at least one forward data line comprises a plurality of forward data lines, and

some of the plurality of forward data lines are turned off by controlling controllable ports of the plurality of neural cores.

10 . The processor of claim 1 , wherein the plurality of neural cores comprises a first set of neural cores and a second set of neural cores,

wherein the first set of neural cores comprises a first neural core and a second neural core,

the second set of neural cores comprises a third neural core and a fourth neural core,

wherein the first set of neural cores are connected in series with each other via a forward data line and a backward data line between the first set of neural cores,

wherein the second set of neural cores are connected in series with each other via a forward data line and a backward data line between the second set of neural cores.

11 . The processor of claim 10 , further comprising a first memory operably coupled to the plurality of neural cores, and

an interconnection through which data are moved,

wherein the first memory, the first set of neural cores, and the second set of neural cores are connected to the interconnection, and

data are moved among the first memory, the first set of neural cores, and the second set of neural cores via the interconnection.

12 . The processor of claim 1 , wherein the plurality of neural cores comprises a first neural core and a second neural core, and

wherein the processor further comprising:

at least one first connection line connected to the at least one forward data line and the first neural core;

at least one second connection line connected to the at least one backward data line and the first neural core;

at least one third connection line connected to the at least one forward data line and the second neural core; and

at least one fourth connection line connected to the at least one backward data line and the second neural core.

13 . The processor of claim 1 , further comprising a first memory operably coupled to the plurality of neural cores, and

wherein the plurality of neural cores are included in a system-on-chip, and

the first memory comprises an off-chip memory external to the system-on-chip.

14 . The processor of claim 1 , wherein the plurality of neural cores comprises a first set of neural cores and a second set of neural cores,

wherein the first set of neural cores comprises a first neural core and a second neural core, the second set of neural cores comprises a third neural core and a fourth neural core, and

a shared memory shared by the first set of neural cores and the second set of neural cores.

15 . The processor of claim 1 , wherein controllable ports of the plurality of neural cores are implemented by software or firmware.

16 . A processor comprising:

a plurality of neural cores comprising a first neural core, a second neural core connected in series with the first neural core in a forward direction, and a third neural core connected in series with the second neural core in the forward direction, each neural core comprising a plurality of controllable ports; and

a first memory connected in series with the first neural core in a backward direction,

a data path for the plurality of neural cores is determined among a plurality of candidate data paths according to a type of a computation performed by the at least one of the plurality of neural cores,

the determined data path is configured on the at least one forward data line and the at least one backward data line by controlling controllable ports of the plurality of neural cores,

wherein the determined data path comprises a data movement path in the forward direction and a data movement path in the backward direction,

the determined data path is configured even when at least one of the first neural core, the second neural core, or the third neural core is inoperative, and

the controlling controllable ports comprises turning on or off at least one controllable port of the controllable ports of the plurality of neural cores,

wherein controlling the controllable ports further comprises:

in association with determining the determined data path, turning on at least one controllable port corresponding to the determined data path and turning off at least one controllable port corresponding to a non-selected data path among the plurality of candidate data paths.

17 . The processor of claim 16 , wherein if the first neural core and the third neural core are operative and the second neural core is inoperative,

the first neural core is provided with first data from the first memory and generates second data by computing the first data,

the second neural core is provided with the second data from the first neural core and provides the second data to the third neural core, and

the third neural core is provided with the second data from the second neural core and generates third data by computing the second data.

18 . The processor of claim 16 , wherein data lines connecting the first neural core to the third neural core comprise a plurality of lines, and

all of the plurality of lines are turned on or some of the plurality of lines are turned off according to a bandwidth of data provided from the first memory.

19 . The processor of claim 16 , further comprising:

a fourth neural core that is not directly connected to the first neural core;

a fifth neural core connected in series with the fourth neural core in the forward direction; and

an interconnection configured to perform data exchange between the first neural core and the fourth neural core.

20 . A method, performed by a processor, for configuring a plurality of data paths of a plurality of neural cores, comprising:

receiving a task including information of the data paths for the plurality of neural cores including a first neural core and a second neural core, and

determining a data path among the plurality of data paths configured on the at least one forward data line and the at least one backward data line by controlling controllable ports of the plurality of neural cores according to a type of a computation performed by the at least one of the plurality of neural cores, and

wherein determining a data path comprises:

configuring a forward data path by turning on a controllable port of the first neural core and a controllable port of the second neural core on the at least one forward data line between the first neural core and the second neural core and data is transmitted via the forward data path from the first neural core to the second neural core, and

configuring a backward data path by turning on a controllable port of the first neural core and a controllable port of the second neural core on the at least one backward data line between the first neural core and the second neural core and data is transmitted via the backward data path from the second neural core to the first neural core, wherein controlling the controllable ports further comprises:

in association with determining the determined data path, turning on at least one controllable port corresponding to the determined data path and turning off at least one controllable port corresponding to a non-selected data path among the plurality of candidate data paths.