Method and apparatus for logarithmic mathematics in AI matrix multiplications
A matrix multiplication system and method are disclosed that perform multiplication in a logarithmic domain and accumulation in a linear domain using co-designed bidirectional conversion circuits. Linear-domain operands are converted to a logarithmic domain by a linear-to-logarithmic conversion that divides a mantissa into exactly four non-uniform windows and applies affine mappings implemented using shift and add operations. Logarithmic-domain multiplication results are converted to linear-domain values by a logarithmic-to-linear conversion that divides a mantissa into exactly four equal-width windows and applies corresponding affine mappings implemented using shift and add operations. The affine mappings of the linear-to-logarithmic conversion are analytic inverses of the affine mappings of the logarithmic-to-linear conversion, and window boundaries of the linear-to-logarithmic conversion are derived by inverse mapping of the logarithmic-to-linear window boundaries. The conversion circuits are co-designed to provide round-trip exactness apart from quantization effects, thereby avoiding systematic bias during accumulation.
1 . A processing system for performing matrix multiplication, comprising:
a matrix multiplication engine comprising a plurality of logarithmic logic cores, each logarithmic logic core configured to perform multiplication in a logarithmic domain and accumulation in a linear domain;
a linear-to-logarithmic conversion circuit positioned upstream of the matrix multiplication engine and shared by the plurality of logarithmic logic cores, the linear-to-logarithmic conversion circuit configured to convert input operand values from the linear domain to the logarithmic domain prior to distribution to the logarithmic logic cores, the linear-to-logarithmic conversion circuit comprising:
a mantissa window selector configured to divide a mantissa range of a linear-domain operand into exactly four non-uniform windows; and
for each of the four non-uniform windows, a corresponding affine mapping implemented using only shift and add operations to generate a logarithmic-domain mantissa value;
a logarithmic-to-linear conversion circuit disposed within each logarithmic logic core and configured to convert logarithmic-domain multiplication results to linear-domain values prior to accumulation, the logarithmic-to-linear conversion circuit comprising:
a mantissa window selector configured to divide a mantissa range [0,1) of a logarithmic-domain value into exactly four equal-width windows, each identifiable based on most-significant mantissa bits; and
for each of the four equal-width windows, a corresponding affine mapping implemented using only shift and add operations to generate a linear-domain mantissa value;
wherein:
each affine mapping of the linear-to-logarithmic conversion circuit is an analytic inverse of a corresponding affine mapping of the logarithmic-to-linear conversion circuit;
non-uniform window boundaries of the linear-to-logarithmic conversion circuit are computed from window boundaries of the logarithmic-to-linear conversion circuit by inverse mapping; and
the linear-to-logarithmic conversion circuit and the logarithmic-to-linear conversion circuit are co-designed such that a round-trip conversion of a mantissa through both conversion circuits is mathematically exact apart from quantization effects, thereby avoiding systematic bias during accumulation within the matrix multiplication engine.
2 . The processing system of claim 1 , wherein the four equal-width windows of the logarithmic-to-linear conversion circuit each span one-quarter of the mantissa range [0,1).
3 . The processing system of claim 1 , wherein the mantissa window selector of the logarithmic-to-linear conversion circuit identifies the four equal-width windows using two most-significant mantissa bits.
4 . The processing system of claim 1 , wherein the non-uniform window boundaries of the linear-to-logarithmic conversion circuit correspond to inverse images of boundary points of the four equal-width windows of the logarithmic-to-linear conversion circuit.
5 . The processing system of claim 4 , wherein the inverse images are computed by algebraic inversion of affine mappings of the logarithmic-to-linear conversion circuit.
6 . The processing system of claim 1 , wherein each affine mapping of the linear-to-logarithmic conversion circuit and its corresponding affine mapping of the logarithmic-to-linear conversion circuit form a bijective pair over a corresponding window.
7 . The processing system of claim 1 , wherein the round-trip conversion preserves monotonic ordering of mantissa values across all four windows.
8 . The processing system of claim 1 , wherein the round-trip conversion introduces no systematic bias in accumulated results across repeated matrix multiplication operations.
9 . The processing system of claim 1 , wherein each affine mapping of the linear-to-logarithmic conversion circuit and the logarithmic-to-linear conversion circuit is implemented without a lookup table and without a general-purpose multiplier.
10 . The processing system of claim 1 , wherein each affine mapping of the linear-to-logarithmic conversion circuit and the logarithmic-to-linear conversion circuit comprises only bit-shift operations, add operations, and subtract operations.
11 . The processing system of claim 1 , wherein coefficients used in affine mappings are powers of two or sums of powers of two.
12 . The processing system of claim 1 , wherein the mantissa corresponds to a mantissa of a floating-point value formatted according to an IEEE-754 standard.
13 . The processing system of claim 12 , wherein the floating-point value is a half-precision floating-point value.
14 . The processing system of claim 1 , wherein exponent values are preserved during conversion and only mantissa values are modified by the linear-to-logarithmic conversion circuit and the logarithmic-to-linear conversion circuit.
15 . The processing system of claim 1 , wherein the linear-to-logarithmic conversion circuit is configured to convert input operands once and distribute converted operands to multiple logarithmic logic cores.
16 . The processing system of claim 1 , wherein each logarithmic logic core comprises a plurality of logarithmic-domain multipliers and a linear-domain adder tree.
17 . The processing system of claim 16 , wherein the logarithmic-to-linear conversion circuit is positioned between the logarithmic-domain multipliers and the linear-domain adder tree.
18 . The processing system of claim 1 , wherein accumulation is performed only in the linear domain.
19 . A method for performing matrix multiplication by a processing system comprising a matrix multiplication engine comprising a plurality of logarithmic logic cores, a linear-to-logarithmic conversion circuit and a logarithmic-to-linear conversion circuit, each logarithmic logic core configured to perform multiplication in a logarithmic domain and accumulation in a linear domain, the method comprising:
converting, by the linear-to-logarithmic conversion circuit comprising a mantissa window selector, wherein the linear-to-logarithmic conversion circuit is positioned upstream of the matrix multiplication engine and shared by the plurality of logarithmic logic cores, input operand values from a linear domain to a logarithmic domain using a linear-to-logarithmic conversion, the linear-to-logarithmic conversion comprising:
dividing, by the mantissa window selector, a mantissa range of each linear-domain operand into exactly four non-uniform windows; and
applying, within each of the four non-uniform windows, a corresponding affine mapping implemented using only shift and add operations to generate a logarithmic-domain mantissa value;
distributing the operand values in logarithmic domain to the plurality of logarithmic logic cores;
within each of the plurality of logarithmic logic cores:
performing multiplication in the logarithmic domain to produce logarithmic-domain multiplication results;
converting, by the logarithmic-to-linear conversion circuit disposed within each logarithmic logic core, the logarithmic-domain multiplication results to linear-domain values using a logarithmic-to-linear conversion, the logarithmic-to-linear conversion comprising:
dividing a mantissa range [0,1) of each logarithmic-domain multiplication result into exactly four equal-width windows; and
applying, within each equal-width window, a corresponding affine mapping implemented using only shift and add operations to generate a linear-domain mantissa value; and
accumulating the linear-domain values;
wherein:
affine mappings used in the linear-to-logarithmic conversion are analytic inverses of corresponding affine mappings used in the logarithmic-to-linear conversion;
boundaries of the four non-uniform windows used in the linear-to-logarithmic conversion are computed from window boundaries of the logarithmic-to-linear conversion by inverse mapping; and
a round-trip conversion of a mantissa from the linear domain to the logarithmic domain and back to the linear domain is mathematically exact apart from quantization effects, thereby avoiding systematic bias during accumulation.
20 . The method of claim 19 , wherein dividing the mantissa range [0,1) into four equal-width windows comprises identifying the four equal-width windows using two most-significant mantissa bits.
21 . The method of claim 19 , wherein computing the boundaries of the four non-uniform windows comprises applying inverse affine mappings to boundary points of the four equal-width windows.
22 . The method of claim 19 , wherein the inverse affine mappings are algebraic inverses of affine mappings used in the logarithmic-to-linear conversion.
23 . The method of claim 19 , wherein each affine mapping of the linear-to-logarithmic conversion and its corresponding inverse affine mapping of the logarithmic-to-linear conversion form a bijective mapping over a corresponding window.
24 . The method of claim 19 , wherein the round-trip conversion preserves monotonic ordering of mantissa values.
25 . The method of claim 19 , wherein the round-trip conversion introduces no systematic bias across repeated matrix multiplication operations.
26 . The method of claim 19 , wherein the affine mappings of the linear-to-logarithmic conversion and the logarithmic-to-linear conversion are implemented without lookup tables and without general-purpose multipliers.
27 . The method of claim 19 , wherein coefficients used in the affine mappings of the linear-to-logarithmic conversion and the logarithmic-to-linear conversion are powers of two or sums of powers of two.
28 . The method of claim 19 , wherein the mantissa corresponds to a mantissa of a floating-point value formatted according to an IEEE-754 standard.
29 . The method of claim 28 , wherein the floating-point value is a half-precision floating-point value.
30 . The method of claim 19 , wherein exponent values are preserved during conversion and only mantissa values are modified.