Mechanism to prevent leakage through side channels in cache memory
A computer-implemented method mitigates side channel attacks in cache memory. The method includes: loading data into a cache line of the cache memory, which includes marking the data as sensitive in metadata of the cache line based on the data being tagged as sensitive; tracking interactions with the data; and determining whether the interactions with the data are not normal based on a preset criteria and the tracked interactions with the data.
1 . A computer-implemented method for mitigating side channel attacks in cache memory, the method comprising:
loading data into a cache line of the cache memory, which comprises marking the data as sensitive in metadata of the cache line in a case that the data is tagged as sensitive;
tracking interactions with the data marked as sensitive in the cache memory without using another memory area for the tracking; and
determining whether the interactions with the data are not normal based on a preset criteria and the tracked interactions with the data.
2 . The method according to claim 1 , further comprising triggering an attack countermeasure based on determining that the interactions with the data are not normal.
3 . The method of claim 1 , wherein the preset criteria is a tolerance parameter setting a number of interactions with the data, and wherein determining whether the interactions with the data are not normal comprises determining that the number of tracked interactions exceeds the tolerance parameter.
4 . The method of claim 1 , wherein the data is used by a first process, and wherein tracking the interactions with the data comprises tracking a number of interactions with the data only by one or more processes different than the first process.
5 . The method of claim 4 , wherein upon loading the data into the cache memory, a process identification field of the metadata in the cache line is set identifying the first process as an owner of the data, and wherein the method further comprises identifying the interactions with the data as done only by one or more of the processes that are different than the first process based on a process identification of an interacting process that is different than that in the process identification field.
6 . The method of claim 4 , wherein the interactions comprise cache loads or cache evictions.
7 . The method of claim 1 , wherein the metadata of the cache line comprises a sensitivity bit, and wherein marking the data as sensitive in the metadata of the cache line comprises setting the sensitivity bit based on the data that is tagged as sensitive.
8 . The method of claim 7 , wherein tracking the interactions with the data is performed only for the data having the sensitivity bit tagged as sensitive and not for other data in the cache memory.
9 . The method of claim 8 , wherein tracking the interactions with the data includes tracking cache evictions and cache loads after the cache evictions, and wherein the preset criteria includes a threshold count of the cache evictions, and wherein the threshold count is defined by a user, preset based on a type of application, or based on historical data.
10 . The method of claim 1 , the method further comprising, prior to loading the data into the cache line:
receiving executable code compiled from source code by a compiler, the source code comprising program data labelled as sensitive by a programmer, the executable code is produced by the compiler such that a computer system executing the code is configured to detect the program data labelled as sensitive in the executable code;
executing the executable code and detecting the program data labelled as sensitive,
wherein the program data labelled as sensitive comprises the data loaded into the cache line.
11 . The method of claim 2 , wherein the attack countermeasure is initiated in an automated manner and impedes an interaction of data belonging to any other process other than a process that has been previously identified as owning the data.
12 . The method of claim 11 , wherein upon triggering the attack counter measure, a randomization of a cache mapping function is executed, wherein the randomization of the cache mapping function includes defining a new mapping function so that a selection of the cache line looks random.
13 . The method of claim 11 , wherein upon triggering the attack counter measure, a partitioning of the cache mapping executed.
14 . The method of claim 11 , wherein upon triggering the attack counter measure, a modification of a cache replacement policy is executed, wherein the modification of the cache replacement policy for the cache memory prevents automatic metadata updating for the cache line.
15 . The method of claim 10 , wherein the source code includes tags provided by the programmer that specify a maximum number of interactions that correspond to the preset criteria.
16 . The method of claim 1 , the method further comprising:
determining second data is not labeled as sensitive;
loading the second data into a second cache line of the cache without marking the second data as sensitive in metadata of the second cache line; and
operating on the second data without tracking interactions with the second data.
17 . The method of claim 1 , wherein, for tracking the interactions with the data, the metadata is initialized using a tracker bit within the metadata.
18 . A processing system comprising one or more hardware processors which, alone or in combination, are configured to provide for execution of a method for mitigating side channel attacks in cache memory, the method comprising:
loading data into a cache line of the cache memory, which comprises marking the data as sensitive in metadata of the cache line in a case that the data is tagged as sensitive;
tracking interactions with the data marked as sensitive in the cache memory without using another memory area for the tracking; and
determining whether the interactions with the data are not normal based on a preset criteria and the tracked interactions with the data.
19 . A tangible, non-transitory computer-readable medium having instructions thereon which, upon execution by one or more hardware processors, alone or in combination, provide for execution of a method for mitigating side channel attacks in cache memory, the method comprising:
loading data into a cache line of the cache memory, which comprises marking the data as sensitive in metadata of the cache line in a case that the data is tagged as sensitive;
tracking interactions with the data marked as sensitive in the cache memory without using another memory area for the tracking; and
determining whether the interactions with the data are not normal based on a preset criteria and the tracked interactions with the data.