Dynamic memory allocation in probing signal states
Disclosed methods and systems include debug circuitry registering candidate sample values in a plurality of sample periods while application circuitry is active. The candidate sample values indicate states of a plurality of candidate signals of the application circuitry. Sample values of first probed signals from each sample period are written to a sample memory using a mapping based on bit-widths of the first probed signals. The sample values of the first probed signals are selected from the candidate sample values. The mapping is updated based on bit-widths of second probed signals, and sample values of the second probed signals from each sample period are written to the sample memory using the mapping. The sample values of the second probed signals are selected from the candidate sample values.
1 . A method comprising:
registering by debug circuitry, candidate sample values in a plurality of sample periods while application circuitry is active, the candidate sample values indicating states of a plurality of candidate signals of the application circuitry;
writing sample values of first probed signals from each sample period to a sample memory using a mapping based on bit-widths of the first probed signals, wherein the sample values of the first probed signals are selected from the candidate sample values;
updating the mapping based on bit-widths of second probed signals; and
writing sample values of the second probed signals from each sample period to the sample memory using the mapping, wherein the sample values of the second probed signals are selected from the candidate sample values.
2 . The method of claim 1 , wherein the mapping indicates a probe depth, and the method further comprising:
limiting writing of the sample values of the first probed signals based on the probe depth; and
wherein updating the mapping includes updating the probe depth in response to input of a changed value of the probe depth.
3 . The method of claim 1 , wherein the mapping indicates first probe depths associated with the first probed signals, respectively, and the method further comprising:
limiting writing of each sample value of the sample values of the first probed signals based on the first probe depths;
wherein updating the mapping includes updating the mapping to indicate second probe depths associated with the second probed signals, respectively, in response to input of the second probe depths; and
limiting writing of each sample value of the sample values of the second probed signals based on the second probe depths.
4 . The method of claim 1 , wherein the writing includes writing one or more sample values of the first probed signals across one or more word address boundaries in response to the mapping indicating a total of bit-widths of the first probed signals being less than or greater than a number of bits in a word of the sample memory.
5 . The method of claim 1 , wherein:
the writing of the sample values of the first probed signals includes writing the sample values of the first probed signals to contiguous bit addresses in the sample memory; and
the writing of the sample values of the second probed signals includes writing the sample values of the second probed signals to contiguous bit addresses in the sample memory.
6 . The method of claim 5 , further comprising, storing, in response to assertion of a trigger signal at one sample period of the plurality of sample periods, values that indicate a word address and a bit column of the sample memory at which the sample values of the first probed signals in the one sample period are written.
7 . The method of claim 1 , wherein writing the sample values of the second probed signals includes writing the sample values of the second probed signals at locations in the sample memory at which the sample values of the first probed signals were written.
8 . The method of claim 1 , wherein:
registering the candidate sample values includes registering the candidate sample values from the application circuitry that is disposed on a semiconductor die; and
writing the sample values of the first probed signals and writing the sample values of the second probed signals includes writing the sample values of the first probed signals and the sample values of the second probed signals to the sample memory that is disposed on the semiconductor die.
9 . The method of claim 1 , wherein:
registering the candidate sample values includes registering the candidate sample values from the application circuitry that is disposed on a first semiconductor die; and
writing the sample values of the first probed signals and writing the sample values of the second probed signals includes writing the sample values of the first probed signals and the sample values of the second probed signals to the sample memory that is disposed on a second semiconductor die.
10 . The method of claim 1 , further comprising, inputting data that identify the second probed signals by the debug circuitry via a scan interface.
11 . A circuit arrangement, comprising:
a sample memory;
a capture circuit configured to register candidate sample values in each sample period of a plurality of sample periods while application circuitry is active, the candidate sample values indicating states of a plurality of candidate signals of the application circuitry; and
a memory manager circuit coupled between the sample memory and the capture circuit and configured to:
write sample values of first probed signals from each sample period to the sample memory using a mapping based on bit-widths of the first probed signals, wherein the sample values of the first probed signals are selected from the candidate sample values,
update the mapping based on bit-widths of second probed signals, and
writing sample values of the second probed signals from each sample period to the sample memory using the mapping, wherein the sample values of the second probed signals are selected from the candidate sample values.
12 . The circuit arrangement of claim 11 , wherein:
the mapping indicates a probe depth;
the memory manager is configured to limit writing of the sample values of the first probed signals based on the probe depth; and
the memory manager is configured to update the probe depth in response to input of a changed value of the probe depth.
13 . The circuit arrangement of claim 11 , wherein:
the mapping indicates first probe depths associated with the first probed signals, respectively; and
the memory manager is configured to:
limit writing of each sample value of the sample values of the first probed signals based on the first probe depths,
update the mapping to indicate second probe depths associated with the second probed signals, respectively, in response to input of the second probe depths, and
limit writing of each sample value of the sample values of the second probed signals based on the second probe depths.
14 . The circuit arrangement of claim 11 , wherein the memory manager is configured to write one or more sample values of the first probed signals across one or more word address boundaries in response to the mapping indicating a total of bit-widths of the first probed signals being less than or greater than a number of bits in a word of the sample memory.
15 . The circuit arrangement of claim 11 , wherein the memory manager is configured to:
write the sample values of the first probed signals to contiguous bit addresses in the sample memory; and
write the sample values of the second probed signals to contiguous bit addresses in the sample memory.
16 . The circuit arrangement of claim 15 , wherein the memory manager is configured to store, in response to assertion of a trigger signal at one sample period of the plurality of sample periods, values that indicate a word address and a bit column of the sample memory at which the sample values of the first probed signals in the one sample period are written.
17 . The circuit arrangement of claim 11 , wherein the memory manager is configured to write the sample values of the second probed signals at locations in the sample memory at which the sample values of the first probed signals were written.
18 . The circuit arrangement of claim 11 , wherein:
the capture circuit is configured to register the candidate sample values from the application circuitry that is disposed on a semiconductor die; and
the sample memory is disposed on the semiconductor die.
19 . The circuit arrangement of claim 11 , wherein:
the capture circuit is configured to register the candidate sample values from the application circuitry that is disposed on a first semiconductor die; and
the sample memory is disposed on a second semiconductor die.
20 . The circuit arrangement of claim 11 , wherein the memory manager is configured to input via a scan interface, data that identify the second probed signals.