Runtime efficient multi-stage router flow for circuit designs

1 . A method, comprising:

generating a hybrid routing graph by detecting input interconnect blocks in a circuit design and representing groups of the input interconnect blocks as a plurality of coarsened routing nodes, wherein the plurality of coarsened routing nodes are independent of one another;

performing, using computer hardware, a global routing of the circuit design using the hybrid routing graph for a target integrated circuit;

wherein the hybrid routing graph includes routing nodes and the plurality of coarsened routing nodes, each coarsened routing node including a plurality of constituent routing nodes of the hybrid routing graph corresponding to the input interconnect blocks that are treated as a single node during the global routing; and

performing, using the computer hardware, a detailed routing of the circuit design to generate a legal routing solution for the circuit design;

wherein the detailed routing is performed by routing, in parallel, nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

2 . The method of claim 1 , wherein the legal routing solution specifies detailed routes of the nets through the plurality of coarsened routing nodes using selected ones of the plurality of constituent routing nodes of the plurality of coarsened routing nodes.

3 . The method of claim 1 , wherein the detailed routing is performed by executing a plurality of Satisfiability (SAT) solvers in parallel.

4 . The method of claim 1 , wherein the detailed routing is performed by executing a plurality of iterative routers in parallel.

5 . The method of claim 1 , wherein the detailed routing is performed by executing a plurality of mappers in parallel, wherein each mapper is configured to select a pre-compiled routing solution from a plurality of pre-compiled routing solutions for a coarsened routing node based on a pin signature of the coarsened routing node.

6 . The method of claim 1 , wherein, for a selected coarsened routing node of the plurality of coarsened routing nodes, one or more input interconnect blocks having feedback are excluded from a group of the input interconnect blocks used to form the selected coarsened routing node.

7 . The method of claim 1 , wherein a solution to the global routing is an illegal routing solution including a plurality of overlapping routes on one or more of the plurality of coarsened routing nodes.

8 . The method of claim 1 , further comprising:

excluding a selected routing node belonging to an interconnect circuit structure from a selected coarsened routing node representing the interconnect circuit structure so that the selected routing node is available for use during the global routing.

9 . A system, comprising:

one or more hardware processors configured to initiate operations including:

generating a hybrid routing graph by detecting input interconnect blocks in a circuit design and representing groups of the input interconnect blocks as a plurality of coarsened routing nodes, wherein the plurality of coarsened routing nodes are independent of one another;

performing a global routing of the circuit design using the hybrid routing graph for a target integrated circuit;

wherein the hybrid routing graph includes routing nodes and the plurality of coarsened routing nodes, each coarsened routing node including a plurality of constituent routing nodes of the hybrid routing graph corresponding to the input interconnect blocks that are treated as a single node during the global routing; and

performing a detailed routing of the circuit design to generate a legal routing solution for the circuit design;

wherein the detailed routing is performed by routing, in parallel, nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.

10 . The system of claim 9 , wherein the legal routing solution specifies detailed routes of the nets through the plurality of coarsened routing nodes using selected ones of the plurality of constituent routing nodes of the plurality of coarsened routing nodes.

11 . The system of claim 9 , wherein the detailed routing is performed by executing a plurality of Satisfiability (SAT) solvers in parallel.

12 . The system of claim 9 , wherein the detailed routing is performed by executing a plurality of mappers in parallel, wherein each mapper is configured to select a pre-compiled routing solution from a plurality of pre-compiled routing solutions for a coarsened routing node based on a pin signature of the coarsened routing node.

13 . The system of claim 9 , wherein, for a selected coarsened routing node of the plurality of coarsened routing nodes, one or more input interconnect blocks having feedback are excluded from a group of the input interconnect blocks used to form the selected coarsened routing node.

14 . The system of claim 9 , wherein a solution to the global routing is an illegal routing solution including a plurality of overlapping routes on one or more of the plurality of coarsened routing nodes.

15 . The system of claim 9 , wherein the one or more hardware processors are configured to initiate operations further comprising:

excluding a selected routing node belonging to an interconnect circuit structure from a selected coarsened routing node representing the interconnect circuit structure so that the selected routing node is available for use during the global routing.

16 . One or more computer-readable storage mediums having program instructions embodied therewith, the program instructions executable by computer hardware to cause the computer hardware to initiate executable operations comprising:

generating a hybrid routing graph by detecting input interconnect blocks in a circuit design and representing groups of the input interconnect blocks as a plurality of coarsened routing nodes, wherein the plurality of coarsened routing nodes are independent of one another;

performing a global routing of the circuit design using the hybrid routing graph for a target integrated circuit;

wherein the hybrid routing graph includes routing nodes and the plurality of coarsened routing nodes, each coarsened routing node including a plurality of constituent routing nodes of the hybrid routing graph corresponding to the input interconnect blocks that are treated as a single node during the global routing; and

performing a detailed routing of the circuit design to generate a legal routing solution for the circuit design;

wherein the detailed routing is performed by routing, in parallel, nets of the circuit design that were globally routed using the plurality of coarsened routing nodes.