Computational neural network apparatus, card, method, and readable storage medium

1 . A method for computing a neural network by using a computing apparatus, the method comprises:

loading an on-chip unit map from an off-chip memory to a ping storage unit, wherein the ping storage unit stores a plurality of on-chip unit maps;

loading an i-th sub-weight in a weight from the off-chip memory to a shared storage unit, wherein

a value of i is a positive integer,

the computing apparatus is connected to the off-chip memory,

the off-chip memory contains the on-chip unit map,

the on-chip unit map corresponds to the weight,

the computing apparatus comprises a plurality of clusters, and

each cluster of the plurality of clusters comprises the shared storage unit and a plurality of processor cores;

broadcasting an i-th sub-map in the on-chip unit map and the i-th sub-weight from the shared storage unit to at least one processor core of the plurality of processor cores;

computing an i-th intermediate result according to the i-th sub-map and the i-th sub-weight, wherein the i-th sub-weight corresponds to the i-th sub-map;

loading an i+1-th sub-weight in the weight from the off-chip memory to the shared storage unit;

broadcasting an i+1-th sub-map in the on-chip unit map from the shared storage unit to at least one processor core of the plurality of processor cores, wherein the i+1-th sub-weight corresponds to the i+1-th sub-map; and

broadcasting the i+1-th sub-weight from the shared storage unit to at least one processor core of the plurality of processor cores after the computation of the i-th intermediate result, wherein a step of loading the i+1-th sub-weight is performed at the same time as the i-th intermediate result is computed.

2 . The method of claim 1 , further comprising:

identifying a sub-weight with a largest storage space in a plurality of sub-weights of the weight; and

determining a size of a weight storage space in the shared storage unit according to the sub-weight with the largest storage space in the plurality of sub-weights.

3 . The method of claim 2 , wherein the i+1-th sub-weight overwrites the i-th sub-weight in the weight storage space.

4 . The method of claim 1 , wherein a step of loading the on-chip unit map and the i-th sub-weight is performed synchronously with a step of loading the i+1-th sub-weight.

5 . The method of claim 4 , further comprises:

storing the i-th sub-weight to a first storage space; and

storing the i+1-th sub-weight to a second storage space, wherein a weight storage space in the shared storage unit comprises the first storage space and the second storage space.

6 . The method of claim 1 , wherein the broadcasting of the i+1-th sub-weight is performed synchronously with the computing of the i-th intermediate result.

7 . The method of claim 6 , further comprises:

storing the i-th sub-weight to a first storage space; and

storing the i+1-th sub-weight to a second storage space, wherein

each processor core of the plurality of processor cores comprises a weight storage unit, and

the weight storage unit comprises the first storage space and the second storage space.

8 . The method of claim 1 , further comprising:

storing the i-th sub-weight to the weight storage unit; and

storing the i+1-th sub-weight to the weight storage unit to overwrite the i-th sub-weight, wherein each processor core of the plurality of processor cores comprises a weight storage unit.

9 . A computing apparatus comprises a plurality of clusters, wherein each cluster of the plurality of clusters comprises:

a shared storage unit;

a direct memory access unit, configured to:

load an on-chip unit map from an off-chip memory to a ping storage unit, wherein the ping storage unit stores a plurality of on-chip unit maps, wherein

the computing apparatus is connected to the off-chip memory, and

the off-chip memory contains an on-chip unit map, and

the on-chip unit map corresponds to a weight;

load an i-th sub-weight in the weight from the off-chip memory to a shared storage unit, wherein the i-th sub-weight is corresponding to the on-chip unit map; and

load an i+1-th sub-weight in the weight from the off-chip memory to the shared storage unit;

a plurality of processor cores, wherein at least one processor core of the plurality of processor cores is configured to compute an i-th intermediate result according to the i-th sub-map and the i-th sub-weight; and

a broadcast bus, configured to:

broadcast an i-th sub-map in the on-chip unit map and the i-th sub-weight from the shared storage unit to at least one of the plurality of processor cores, wherein the i-th sub-weight corresponds to the i-th sub-map;

broadcast an i+1-th sub-map in the on-chip unit map from the shared storage unit to the at least one processor core of the plurality of processor cores, wherein the i+1-th sub-weight corresponds to the i+1-th sub-map; and

broadcast the i+1-th sub-weight from the shared storage unit to at least one of the plurality of processor cores after the computation of the i-th intermediate result, wherein a step of loading the i+1-th sub-weight is performed at the same time as the i-th intermediate result is computed.

10 . The computing apparatus of claim 9 , wherein the computing apparatus is further configured to determine a size of a weight storage space in the shared storage unit according to a sub-weight with the largest storage space in the plurality of sub-weights.

11 . The computing apparatus of claim 10 , wherein the i+1-th sub-weight overwrites the i-th sub-weight in the weight storage space.

12 . The computing apparatus of claim 9 , wherein when the direct memory access unit loads the on-chip unit map and the i-th sub-weight, the direct memory access unit synchronously loads the i+1-th sub-weight.

13 . The computing apparatus of claim 12 , wherein the weight storage space in the shared storage unit comprises:

first storage space, configured to store the i-th sub-weight; and

second storage space, configured to store the i+1-th sub-weight.

14 . The computing apparatus of claim 9 , wherein when the at least one of the plurality of processor cores computes the i-th intermediate result, the broadcast bus synchronously broadcasts the i+1-th sub-weight.

15 . The computing apparatus of claim 14 , wherein

each processor core of the of the plurality of processor cores comprises a weight storage unit, and

the weight storage unit comprises:

a first storage space, configured to store the i-th sub-weight; and

a second storage space, configured to store the i+1-th sub-weight.

16 . The computing apparatus of claim 9 , wherein

each processor core of the plurality of processor cores comprises a weight storage unit configured to store the i-th sub-weight and the i+1-th sub-weight, and

the i+1-th sub-weight overwrites the i-th sub-weight.