IP Library Granted Patent US 12688461
Granted Patent B2
US 12688461 · App. 18/250,517 · Granted Jul 21, 2026

Reconfigurable computing fabric for machine learning processing

Inventors: Ravi Shankar Subramaniam (Palo Alto, CA); Robert Campbell (Palo Alto, CA); Jeffrey Kevin Jeansonne (Spring, TX); Lan Wang (Spring, TX); Christopher Charles Mohrman (Spring, TX)
Assignee: Hewlett-Packard Development Company, L.P.
G06N20/00
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Quick Facts
Patent No.
US 12688461
App. No.
18/250,517
Granted
Jul 21, 2026
Kind
B2
Abstract

One example provides a reconfigurable computing fabric to manage machine learning (ML) processing including a configurable interconnect structure and a number programmable logic blocks each having a configurable set of operations. For each of a number of fabric configurations of the computing fabric, each programmable logic block has a corresponding set of operations and the interconnect structure has a corresponding data path structure to interconnect the programmable logic blocks with one another and with inputs and outputs of the computing fabric. The programmable logic blocks include an input/output block having a set of operations including to provide virtual interfaces to receive external session requests for ML processing from request sources, and an elastic AI/ML processing block having a set of operations including to configure a number of AI/ML engines with a session implementation for each external session request and each of a number of event-driven internal session requests.

Claims (51)

1 . A reconfigurable computing fabric to manage machine learning (ML) processing, the computing fabric comprising:

a configurable interconnect structure of a field programmable gate array (FPGA); and

a number of programmable logic blocks of the FPGA each having a configurable set of operations, wherein for each of a number of fabric configurations of the computing fabric, each programmable logic block has a corresponding set of operations and the interconnect structure has a corresponding data path structure to interconnect the programmable logic blocks with one another and with inputs and outputs of the computing fabric, and wherein the programmable logic blocks of the FPGA include:

an input/output block having a set of operations including to:

provide customizable virtual input interfaces to receive external session requests for ML processing from a number of request sources; and

an elastic artificial intelligence (AI) processing block having a set of operations including to:

configure a number of AI/ML engines with a session implementation for each external session request and each of a number of event-driven internal session requests; and

direct input data for each external and each internal session request to the AI/ML engines configured with the corresponding session implementation for processing.

2 . The computing fabric of claim 1 , wherein the configurable set of operations of each programmable logic block is based on a hardware and software setup of the programmable logic block where the hardware and software setup is different for each fabric configuration.

3 . The computing fabric of claim 1 , wherein each session implementation is based on processing requirements of the corresponding session request and on a set of operating policies.

4 . The computing fabric of claim 1 , wherein the session implementation includes loading ML models onto the AI/ML engines based on the corresponding session request and a set of operating policies.

5 . The computing fabric of claim 1 , the elastic AI processing block including a session implementation state block to maintain a state of each session implementation for each session.

6 . The computing fabric of claim 1 , the set of operations of the input/output block further including to provide customizable virtual source interfaces with a number of input sources which are selected based on a session request, each virtual source interface to provide input data for the corresponding session request.

7 . The computing fabric of claim 6 , the input/output block including a session interface state block to maintain a state of each virtual input interface and each virtual source interface for a life of each session.

8 . The computing fabric of claim 6 , the input sources including a number of sensors each providing input data representative of a measured feature, the programmable logic blocks further including an elastic sensor management block including a dynamic sensor functionality block and a sensor fungibility block to manage data provided by the sensors.

9 . The computing fabric of claim 8 , the dynamic sensor functionality block including a set of operations to transform data from one or more physical sensors to dynamically form a virtual sensor providing an output representative of a feature different from a feature measured by the one or more physical sensors, the sensor fungibility block including a set of operations to select an input data representative of a same feature from multiple sensors, including from physical and dynamically formed virtual sensors, providing the same feature based on a set of operating policies.

10 . A dynamically configurable machine learning (ML) platform comprising:

a reconfigurable computing fabric configurable to a number of fabric configurations, the computing fabric comprising:

a configurable interconnect structure of a field programmable gate array (FPGA); and

a number of programmable logic blocks of the FPGA each having a configurable set of operations, wherein for each fabric configuration, each programmable logic block has a corresponding set of operations and the interconnect structure has a corresponding data path structure to interconnect the programmable logic blocks with one another and with inputs and outputs of the computing fabric, and wherein the programmable logic blocks of the FPGA include:

an input/output block having a set of operations including to:

provide customizable virtual input interfaces to receive external session requests for ML processing from a number of request sources; and

an elastic artificial intelligence (AI) processing block having a set of operations including to:

configure a number of AI/ML engines with a session implementation for each external session request and each of a number of event-driven internal session requests; and

direct input data for each external and each internal session request to the AI/ML engines configured with the corresponding session implementation for processing; and

a supervisory controller to configure the computing fabric to a selected one of the number of fabric configurations.

11 . The ML platform of claim 10 , including:

the number of AI/ML engines; and

a number of sensors, each sensor providing input data representative of a feature.

12 . The ML platform of claim 11 , the set of operations of the input/output block including to provide customizable virtual source interfaces with a number of input sources based on a session request, the input sources including the number of sensors, each virtual source interface to provide input data for the corresponding session request.

13 . The ML platform of claim 12 , the programmable logic blocks including an elastic sensor management block having:

a dynamic sensor functionality block including a set of operations to transform data representative of a measured feature from one or more physical sensors to dynamically form a virtual sensor providing input data representative of a feature different from the measured feature; and

a sensor fungibility block including a set of operations to select input data representative of a given feature from multiple sensors providing the given feature, including from physical sensors and dynamically formed virtual sensors.

14 . A device comprising:

a central processing unit (CPU) running an operating system; and

a dynamically configurable machine learning (ML) platform including:

a reconfigurable computing fabric configurable to a number of fabric configurations, the computing fabric comprising:

a configurable interconnect structure of a field programmable gate array (FPGA); and

a number of programmable logic blocks of the FPGA each having a configurable set of operations, wherein for each fabric configuration, each programmable logic block has a corresponding set of operations and the interconnect structure has a corresponding data path structure to interconnect the programmable logic blocks with one another and with inputs and outputs of the computing fabric, and wherein the programmable logic blocks of the FPGA include:

an input/output block having a set of operations including to:

 provide customizable virtual input interfaces to receive external session requests for ML processing from a number of request sources, including the operating system running on the CPU; and

an elastic artificial intelligence (AI) processing block having a set of operations including to:

 configure a number of AI/ML engines with a session implementation for each external session request and each of a number of event-driven internal session requests; and

 direct input data for each external and each internal session request to the AI/ML engines configured with the corresponding session implementation for processing; and

a supervisory controller to configure the computing fabric to a selected one of the number of fabric configurations.

15 . The computing fabric of claim 1 , wherein the number of request sources comprise an operating system running on a central processing unit (CPU).

16 . The computing fabric of claim 15 , wherein the programmable logic blocks of the FPGA are to operate in an active state to enable continued execution of at least one ML model on the AI/ML engines while the operating system is in a sleep, hibernate, or off mode.

17 . The computing fabric of claim 1 , wherein the elastic AI processing block is to partition a ML model onto the AI/ML engines and cause processing of the partitioned ML model on the AI/ML engines in parallel.

18 . The computing fabric of claim 1 , wherein the AI/ML engines comprise at least one AI/ML engine instantiated on the computing fabric and at least one AI/ML engine instantiated outside of the computing fabric.

19 . The computing fabric of claim 1 , wherein the programmable logic blocks of the FPGA are to direct a plurality of signals output by sensors to respectively corresponding AI/ML engines.

20 . The device of claim 14 , wherein the supervisory controller is a microcontroller external to the FPGA.