Gate driving circuit and display device

1 . A gate driving circuit, comprising:

a first node control circuit configured to control a voltage level of a first node;

a first maintaining circuit configured to maintain the voltage level of the first node according to a voltage level of a second node;

a first output circuit configured to output a gate signal from a gate signal output terminal according to the voltage level of the first node; and

a first node voltage-stabilizing circuit configured to be turned on, during a touch stage, according to a first level of a touch signal to control the voltage level of the second node, such that the first maintaining circuit is turned off to stabilize the voltage level of the first node, wherein the touch signal is input from a touch signal input terminal.

2 . The gate driving circuit according to claim 1 , wherein the first node voltage-stabilizing circuit is further configured to be turned off, during a display stage, according to a second level of the touch signal, and the second level is less than the first level.

3 . The gate driving circuit according to claim 2 , wherein the first node voltage-stabilizing circuit comprises a first node voltage-stabilizing transistor, a source and a drain of the first node voltage-stabilizing transistor are connected between the second node and a first voltage input terminal, and a gate of the first node voltage-stabilizing transistor is connected to the touch signal input terminal.

4 . The gate driving circuit according to claim 1 , wherein the first maintaining circuit comprises a first maintaining transistor, a source and a drain of the first maintaining transistor are connected between the first node and the touch signal input terminal, and a gate of the first maintaining transistor is connected to the second node.

5 . The gate driving circuit according to claim 1 , further comprising a reset circuit, wherein during a display stage, the reset circuit is configured to connect the first node with the touch signal input terminal according to a third level of a reset signal to reset the voltage level of the first node, and the reset signal is input from a reset signal input terminal; and/or,

wherein during the touch stage, the reset circuit is further configured to disconnect the first node from the touch signal input terminal according to a fourth level of the reset signal, and the fourth level is less than the third level.

6 . The gate driving circuit according to claim 5 , wherein the reset circuit comprises a reset transistor, a source and a drain of the reset transistor are connected between the first node and the touch signal input terminal, and a gate of the reset transistor is connected to the reset signal input terminal.

7 . The gate driving circuit according to claim 1 , further comprising a second maintaining circuit, wherein during a display stage, the second maintaining circuit is configured to connect the touch signal input terminal with the first node according to a fifth level of a first stage transmission signal to maintain the voltage level of the first node, and the first stage transmission signal is input from a first stage transmission signal input terminal; and/or,

wherein during the touch stage, the second maintaining circuit is further configured to disconnect the first node from the touch signal input terminal according to a sixth level of the first stage transmission signal, and the sixth level is less than the fifth level.

8 . The gate driving circuit according to claim 7 , wherein the second maintaining circuit comprises a second maintaining transistor, a source and a drain of the second maintaining transistor are connected between the first node and the touch signal input terminal, and a gate of the second maintaining transistor is connected to the first stage transmission signal input terminal.

9 . The gate driving circuit according to claim 1 , further comprising a second node control circuit, wherein the second node control circuit is configured, according to the voltage level of the first node, to make a phase of the voltage level of the second node to be opposite to a phase of the voltage level of the first node.

10 . The gate driving circuit according to claim 9 , wherein the second node control circuit comprises a first transistor and a second transistor;

wherein a source and a drain of the first transistor are connected between the second node and a second voltage input terminal, and a gate of the first transistor is connected to the second voltage input terminal; and

wherein a source and a drain of the second transistor are connected between the second node and a first voltage input terminal, and a gate of the second transistor is connected to the first node.

11 . The gate driving circuit according to claim 10 , wherein the second node control circuit further comprises a third transistor, a source and a drain of the third transistor are connected between the second node and the first voltage input terminal, and a gate of the third transistor is connected to a second stage transmission signal input terminal.

12 . The gate driving circuit according to claim 1 , wherein the first node control circuit comprises a first node control transistor, a source and a drain of the first node control transistor are connected between the first node and a second stage transmission signal input terminal or an initial signal input terminal, and a gate of the first node control transistor is connected to the second stage transmission signal input terminal or the initial signal input terminal; and/or,

wherein the first output circuit comprises a first output transistor, a source and a drain of the first output transistor are connected between a clock signal input terminal and the gate signal output terminal, the clock signal input terminal is configured to input an input clock signal, and a gate of the first output transistor is connected to the first node; and/or,

wherein the first output circuit comprises a second output transistor, a source and a drain of the second output transistor are connected between a first voltage input terminal and the gate signal output terminal, the first voltage input terminal is configured to input a first level signal, a gate of the second output transistor is connected to a first stage transmission signal input terminal, and the first stage transmission signal input terminal is configured to input the first stage transmission signal; and/or,

wherein the gate driving circuit further comprises a capacitor, and two electrodes of the capacitor are connected between the first node and the gate signal output terminal.

13 . The gate driving circuit according to claim 1 , further comprising a third maintaining circuit, wherein the third maintaining circuit is configured, according to the voltage level of the second node, to maintain a voltage level of the gate signal output terminal.

14 . The gate driving circuit according to claim 13 , wherein the third maintaining circuit comprises a third maintaining transistor, a source and a drain of the third maintaining transistor are connected between the gate signal output terminal and a first voltage input terminal, and a gate of the third maintaining transistor is connected to the second node.

15 . The gate driving circuit according to claim 1 , further comprising a second output circuit, wherein the second output circuit is configured, according to the voltage level of the first node, to output a third stage transmission signal from a third stage transmission signal output terminal.

16 . The gate driving circuit according to claim 15 , further comprising a fourth maintaining circuit, wherein the fourth maintaining circuit is configured, according to the level voltage of the second node, to maintain a voltage level of the third stage transmission signal output terminal.

17 . The gate driving circuit according to claim 16 , wherein the second output circuit comprises a third output transistor, a source and a drain of the third output transistor are connected between the third stage transmission signal output terminal and a clock signal input terminal, and a gate of the third output transistor is connected to the first node; and/or,

wherein the fourth maintaining circuit comprises a fourth maintaining transistor, a source and a drain of the fourth maintaining transistor are connected between the third stage transmission signal output terminal and a first voltage input terminal, and a gate of the fourth maintaining transistor is connected to the second node.

18 . The gate driving circuit according to claim 1 , further comprising a touch voltage-stabilizing circuit, wherein during the touch stage, the touch voltage-stabilizing circuit is configured to be turned on according to the first level of the touch signal to stabilize a voltage level of the gate signal output terminal; wherein during the display stage, the touch voltage-stabilizing circuit is further configured to be turned off according to a second level of the touch signal, and the second level is less than the first level.

19 . The gate driving circuit according to claim 18 , wherein the touch voltage-stabilizing circuit comprises a touch voltage-stabilizing transistor, a source and a drain of the touch voltage-stabilizing transistor are connected between the gate signal output terminal and a first voltage input terminal, and a gate of the touch voltage-stabilizing transistor is connected to the touch signal input terminal.

20 . A display device, comprising a gate driving circuit, wherein the gate driving circuit, comprising:

a first node control circuit configured to control a voltage level of a first node;

a first maintaining circuit configured to maintain the voltage level of the first node according to a voltage level of a second node;

a first output circuit configured to output a gate signal from a gate signal output terminal according to the voltage level of the first node; and

a first node voltage-stabilizing circuit configured to be turned on, during a touch stage, according to a first level of a touch signal to control the voltage level of the second node, such that the first maintaining circuit is turned off to stabilize the voltage level of the first node, wherein the touch signal is input from a touch signal input terminal.