Pixel circuit, display panel, and display device with reduced flickering of image
A pixel circuit, a display panel, and a display device are provided. The pixel circuit includes a driving module and a bias compensation module. A control terminal of the bias compensation module is electrically connected to a first control signal line, a first terminal of the bias compensation module is electrically connected to a target signal line, a second terminal of the bias compensation module is electrically connected to a first terminal of the driving module or a second terminal of the driving module, and the target signal line is electrically connected to a first periodic signal.
1 . A pixel circuit, comprising:
a driving module;
a bias compensation module, wherein a control terminal of the bias compensation module is electrically connected to a first control signal line, a first terminal of the bias compensation module is electrically connected to a target signal line, a second terminal of the bias compensation module is electrically connected to a first terminal of the driving module or a second terminal of the driving module, and the target signal line is electrically connected to a first periodic signal;
a first reset module, wherein a control terminal of the first reset module is electrically connected to a first scan control signal line, a first terminal of the first reset module is electrically connected to a first reference voltage signal line, and a second terminal of the first reset module is electrically connected to a first node; and
a threshold compensation module, wherein a control terminal of the threshold compensation module is electrically connected to a third scan control signal line, a first terminal of the threshold compensation module is electrically connected to the first node, and a second terminal of the threshold compensation module is electrically connected to the second terminal of the driving module,
wherein:
the first reset module and the threshold compensation module each include an N-type transistor.
2 . The pixel circuit according to claim 1 , further comprising:
a first bias compensation phase and a second bias compensation phase,
wherein:
in the first bias compensation phase and the second bias compensation phase, the bias compensation module is turned on; and
polarities and/or amplitudes of the first periodic signal in the first bias compensation phase and the second bias compensation phase are different.
3 . The pixel circuit according to claim 1 , further comprising:
a first bias compensation phase and a second bias compensation phase,
wherein:
in the first bias compensation phase and the second bias compensation phase, the bias compensation module is turned on; and
polarities of the first periodic signal in the first bias compensation phase and the second bias compensation phase are same.
4 . The pixel circuit according to claim 1 , further comprising:
a light emitting control signal line and a scan control signal line,
wherein
the target signal line multiplexes the scan control signal line; or
the light emitting control signal line of a non-self pixel circuit of the pixel circuit.
5 . The pixel circuit according to claim 4 , further comprising:
a first reset module and a data writing module,
wherein:
a control terminal of the first reset module is electrically connected to a first scan control signal line, and a control terminal of the data writing module is electrically connected to a second scan control signal line;
the target signal line multiplexes the light emitting control signal line of a non-self pixel circuit of the pixel circuit; and
a signal period of the light emitting control signal line is same as a signal period of the first scan control signal line and/or the second scan control signal line.
6 . The pixel circuit according to claim 1 ,
wherein the first node is electrically connected to a control terminal of the driving module, and the first control signal line multiplexes the first scan control signal line.
7 . The pixel circuit according to claim 1 , further comprising:
a first bias compensation phase and a second bias compensation phase, wherein in the first bias compensation phase and the second bias compensation phase, the bias compensation module is turned on;
a data writing module, wherein a control terminal of the data writing module is electrically connected to a second scan control signal line, a first terminal of the data writing module is electrically connected to a data signal line, and a second terminal of the data writing module is electrically connected to the first terminal of the driving module; and
a first data writing phase and a second data writing phase, wherein in the first data writing phase and the second data writing phase, the data writing module is turned on, writing data signals of the data signal line into the first terminal of the driving module, wherein the first data writing phase is located between the first bias compensation phase and the second bias compensation phase, and the second bias compensation phase is located between the first data writing phase and the second data writing phase.
8 . The pixel circuit according to claim 1 , further comprising:
a first reset module and a data writing module,
wherein:
a control terminal of the first reset module is electrically connected to a first scan control signal line;
a control terminal of the data writing module is electrically connected to a second scan control signal line, a first terminal of the data writing module is electrically connected to a data signal line, and a second terminal of the data writing module is electrically connected to the first terminal of the driving module; and
the target signal line multiplexes the first scan control signal line or the second scan control signal line.
9 . The pixel circuit according to claim 8 , wherein:
the target signal line multiplexes the second scan control signal line; and
in at least one data writing phase of a data writing phase, the bias compensation module is turned on, the data writing module is turned on, and a voltage value of a second scan control signal provided by the second scan control signal line is same as a voltage value of a data signal provided by the data signal line.
10 . The pixel circuit according to claim 1 , wherein:
the bias compensation module includes an N-type transistor; and
the first control signal line multiplexes the first scan control signal line or the third scan control signal line.
11 . The pixel circuit according to claim 1 , further comprising:
a data writing module, wherein a control terminal of the data writing module is electrically connected to a second scan control signal line, a first terminal of the data writing module is electrically connected to a data signal line, and a second terminal of the data writing module is electrically connected to the first terminal of the driving module,
wherein:
the bias compensation module and the data writing module each include a P-type transistor; and
the first control signal line multiplexes the second scan control signal line.
12 . A display panel, comprising:
a plurality of rows of pixel circuits, wherein each row of the plurality of rows of pixel circuits includes a pixel circuit, wherein the pixel circuit includes:
a driving module;
a bias compensation module, wherein a control terminal of the bias compensation module is electrically connected to a first control signal line, a first terminal of the bias compensation module is electrically connected to a target signal line, a second terminal of the bias compensation module is electrically connected to a first terminal of the driving module or a second terminal of the driving module, and the target signal line is electrically connected to a first periodic signal;
a first reset module, wherein a control terminal of the first reset module is electrically connected to a first scan control signal line, a first terminal of the first reset module is electrically connected to a first reference voltage signal line, and a second terminal of the first reset module is electrically connected to a first node; and
a threshold compensation module, wherein a control terminal of the threshold compensation module is electrically connected to a third scan control signal line, a first terminal of the threshold compensation module is electrically connected to the first node, and a second terminal of the threshold compensation module is electrically connected to the second terminal of the driving module,
wherein:
the first reset module and the threshold compensation module each include an N-type transistor.
13 . The display panel according to claim 12 , wherein:
the display panel includes M rows of pixel circuits and N light emitting control signal lines, a light emitting control signal line of the N light emitting control signal lines corresponds to a row of pixel circuits of the M rows of pixel circuits, the light emitting control signal line is electrically connected to a light emitting control module in the pixel circuit, wherein N and M are positive integers, with N>M; and
the target signal line connected to the bias compensation module in an i-th row of pixel circuits of the M rows of pixel circuits multiplexes the light emitting control signal line correspondingly connected to a j-th row of pixel circuits of the M rows of pixel circuits, where i and j are positive integers, with i≠j, 1≤i≤M, and 1≤j≤M.
14 . The display panel according to claim 13 , wherein:
the j-th row of pixel circuits and the i-th row of pixel circuits are separated by k rows of pixel circuits of the M rows of pixel circuits, where k is a positive integer.
15 . The display panel according to claim 14 , wherein:
along a first direction pointing from a first edge to a second edge of the display panel, a first row of pixel circuits to an M-th row of pixel circuits are arranged in sequence, and the j-th row of pixel circuits is on a side of the i-th row of pixel circuits close to the first edge.
16 . The display panel according to claim 15 , wherein:
N≥M+k;
the light emitting control signal lines extend along a second direction, and along the first direction pointing from the first edge to the second edge of the display panel, a first light emitting control signal line to an N-th light emitting control signal line are sequentially arranged, and the first direction intersects the second direction; and
at least k light emitting control signal lines near the first edge of the display panel are not electrically connected to the light emitting control modules in the pixel circuits, and the first row of pixel circuits to a k-th row of pixel circuits are electrically connected to k light emitting control signal lines of the at least k light emitting control signal lines near the first edge of the display panel respectively, wherein one row of pixel circuits is electrically connected to one light emitting control signal line; or at least k light emitting control signal lines near the second edge of the display panel are not electrically connected to the light emitting control modules in the pixel circuits, and an (M-k+1)-th row of pixel circuits to the M-th row of pixel circuits are electrically connected to k light emitting control signal lines of the at least k light emitting control signal lines near the second edge of the display panel respectively, wherein one row of pixel circuits is electrically connected to one light emitting control signal line.
17 . The display panel according to claim 16 , further comprising:
an impedance compensation module, wherein the impedance compensation module is electrically connected to the at least k light emitting control signal lines near the first edge of the display panel.
18 . The display panel according to claim 17 , wherein:
a light emitting control signal line of the at least k additional light emitting control signal lines is electrically connected to at least one impedance compensation module of the impedance compensation module.
19 . A display device, comprising a display panel, wherein:
the display panel includes a plurality of rows of pixel circuits, and each row of the plurality of rows of pixel circuits includes a pixel circuit, wherein the pixel circuit includes:
a driving module;
a bias compensation module, wherein a control terminal of the bias compensation module is electrically connected to a first control signal line, a first terminal of the bias compensation module is electrically connected to a target signal line, a second terminal of the bias compensation module is electrically connected to a first terminal of the driving module or a second terminal of the driving module, and the target signal line is electrically connected to a first periodic signal;
a first reset module, wherein a control terminal of the first reset module is electrically connected to a first scan control signal line, a first terminal of the first reset module is electrically connected to a first reference voltage signal line, and a second terminal of the first reset module is electrically connected to a first node; and
a threshold compensation module, wherein a control terminal of the threshold compensation module is electrically connected to a third scan control signal line, a first terminal of the threshold compensation module is electrically connected to the first node, and a second terminal of the threshold compensation module is electrically connected to the second terminal of the driving module,
wherein:
the first reset module and the threshold compensation module each include an N-type transistor.