Light emitting pixel circuit comprising small number of transistors driven by pulse width modulation performing internal compensation of threshold voltage
A pixel circuit includes a first transistor, a second transistor for applying a data voltage to the first transistor, a third transistor for diode-connecting the first transistor, a fourth transistor for applying a first power voltage to a first electrode of the first transistor, a fifth transistor for connecting a second electrode of the first transistor and a fourth node, a sixth transistor for applying an initialization voltage, a seventh transistor, an eighth transistor for applying the data voltage to a fifth node in response to a second scan signal, a tenth transistor for applying a second power voltage to the fifth node, a twelfth transistor for applying the initialization voltage to the fourth node and a light emitting element. A sweep signal is applied to a control electrode of the first transistor, and the sweep signal is a global signal which has same timing across at least two pixel-rows.
1 . A pixel circuit comprising:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor configured to apply a data voltage to the second node in response to a first scan signal;
a third transistor configured to connect the first node and the third node in response to the first scan signal;
a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal;
a fifth transistor configured to connect the third node and a fourth node in response to the emission signal;
a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal;
a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node and a second electrode connected to a sixth node and configured to generate a driving current;
an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal;
a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal;
a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and
a light emitting element configured to emit light based on the driving current,
wherein the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor and the eighth transistor are N-type transistors, and
wherein a sweep signal is applied to the first node, and the sweep signal is a global signal which has a same timing across at least two pixel-rows.
2 . The pixel circuit of claim 1 , wherein the second scan signal, the emission signal, the first initialization signal and the second initialization signal are the global signal.
3 . The pixel circuit of claim 1 , further comprising:
a ninth transistor configured to connect the fourth node and the sixth node in response to the second scan signal;
an eleventh transistor configured to connect the sixth node and a seventh node in response to the emission signal; and
a thirteenth transistor configured to apply a light emitting element initialization voltage to a first electrode of the light emitting element in response to a light emitting element initialization signal.
4 . The pixel circuit of claim 3 , wherein the light emitting element initialization signal is the global signal.
5 . The pixel circuit of claim 3 , wherein the light emitting element includes the first electrode connected to the seventh node and a second electrode configured to receive a third power voltage, and
wherein the light emitting element initialization voltage is lower than the third power voltage.
6 . The pixel circuit of claim 3 , wherein the fourth transistor, the fifth transistor, the tenth transistor, the eleventh transistor and the thirteenth transistor are P-type transistors, and the sixth transistor, the ninth transistor and the twelfth transistor are N-type transistors.
7 . The pixel circuit of claim 1 , wherein in an emission-on period, the first transistor is turned off, and the light emitting element emits light while the seventh transistor is turned on, and
wherein in an emission-off period following the emission-on period, when the first transistor is turned on, the seventh transistor is turned off and the light emitting element stops emitting light.
8 . The pixel circuit of claim 1 , wherein in a first period of a frame period in which the pixel circuit is driven, the first initialization signal has an activation level, the second initialization signal has an activation level and the sweep signal has a high level, and the sixth transistor is turned on and the twelfth transistor is turned on.
9 . The pixel circuit of claim 8 , wherein in a second period following the first period, the data voltage has a pulse width data voltage, the first initialization signal has an inactivation level, the second initialization signal has an inactivation level, the first scan signal has an activation level, the second transistor is turned on, and the third transistor is turned on.
10 . The pixel circuit of claim 9 , wherein in a third period following the second period, the data voltage has a constant current voltage, the first scan signal has an inactivation level, the second scan signal has an activation level, and the eighth transistor is turned on.
11 . The pixel circuit of claim 10 , wherein in a fourth period following the third period, the emission signal has an activation level, the sweep signal is decreased from the high level to a low level lower than the high level.
12 . The pixel circuit of claim 1 , wherein a frame period in which the pixel circuit is driven includes a writing frame in which a pulse width data voltage is applied to the pixel circuit and the light emitting element emits light and a holding frame in which the pulse width data voltage is not applied to the pixel circuit and the light emitting element emits light.
13 . The pixel circuit of claim 12 , wherein in a first holding period of the holding frame, the sweep signal has a high level, the first initialization signal has an inactivation level, the second initialization signal has an activation level, the emission signal has an inactivation level, the sixth transistor is turned off and the twelfth transistor is turned on.
14 . The pixel circuit of claim 13 , wherein in a second holding period following the first holding period, the second initialization signal has an inactivation level, the first scan signal has an inactivation level, and the twelfth transistor is turned off.
15 . The pixel circuit of claim 14 , wherein in a third holding period following the second holding period, the data voltage has a constant current voltage, the second scan signal has an activation level, and the eighth transistor is turned on.
16 . The pixel circuit of claim 15 , wherein in a fourth holding period following the third holding period, the emission signal has an activation level, the sweep signal is decreased from the high level to a low level lower than the high level.
17 . The pixel circuit of claim 16 , wherein in the first holding period to the fourth holding period, the data voltage has the constant current voltage, and the first scan signal has the inactivation level.
18 . The pixel circuit of claim 16 , wherein in the first holding period to the fourth holding period, the first initialization signal has the inactivation level.
19 . A display apparatus comprising:
a display panel including a pixel circuit, a display region, a first peripheral region and a second peripheral region;
a gate driver configured to apply a first scan signal to the display region;
a data driver configured to apply a data voltage to the display region;
a voltage generator configured to apply a global signal which has a same timing across at least two pixel-rows to the display region; and
a driving controller configured to control the gate driver, the data driver and the voltage generator,
wherein the pixel circuit includes:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor configured to apply the data voltage to the second node in response to a first scan signal;
a third transistor configured to connect the first node and the third node in response to the first scan signal;
a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal;
a fifth transistor configured to connect the third node and a fourth node in response to the emission signal;
a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal;
a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node and a second electrode connected to a sixth node and configured to generate a driving current;
an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal;
a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal;
a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and
a light emitting element configured to emit light based on the driving current,
wherein the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor and the eighth transistor are N-type transistors, and
wherein a sweep signal is applied to the first node, and the sweep signal is the global signal.
20 . The display apparatus of claim 19 , wherein the voltage generator applies a gate clock signal to the gate driver, and applies the emission signal, the first initialization signal, the second initialization signal, the second scan signal and the sweep signal to the display region.
21 . The display apparatus of claim 20 , wherein the gate driver is disposed on the first peripheral region,
the display region is disposed between the first peripheral region and the second peripheral region, and
wherein an emission line configured to receive the emission signal, a first initialization line configured to receive the first initialization signal, a second initialization line configured to receive the second initialization signal, a second scan signal line configured to receive the second scan signal and a sweep signal line configured to receive the sweep signal are disposed on the second peripheral region.
22 . A pixel circuit comprising:
a light emitting element;
a pulse width driving circuit configured to generate a pulse width signal; and
a constant current driving circuit configured to control an emission of the light emitting element based on the pulse width signal,
wherein the pulse width driving circuit includes:
a pulse driving transistor configured to generate the pulse width signal based on a sweep signal which is a global signal that has a same timing across at least two pixel-rows;
a pulse writing transistor configured to apply a data voltage to a first electrode of the pulse driving transistor in response to a first scan signal which is a progressive signal that has a different timing across the at least two pixel-rows;
a pulse emission control transistor configured to apply a first power voltage to the first electrode of the pulse driving transistor in response to an emission signal; and
a first initialization transistor configured to apply an initialization voltage to a control electrode of the pulse driving transistor in response to a first initialization signal,
wherein the constant current driving circuit includes:
a constant current driving transistor configured to apply a driving current to the light emitting element in response to the pulse width signal;
a constant current writing transistor configured to apply a constant current voltage to a first electrode of the constant current driving transistor in response to a second scan signal;
a constant current emission control transistor configured to apply a second power voltage to the first electrode of the constant current driving transistor in response to the emission signal; and
a second initialization transistor configured to apply the initialization voltage to a control electrode of the constant current driving transistor in response to a second initialization signal, and
wherein the pulse driving transistor and the constant current driving transistor are P-type transistors and the pulse writing transistor and the constant current writing transistor are N-type transistors.
23 . The pixel circuit of claim 22 , wherein the emission signal, the first initialization signal, the second initialization signal and the second scan signal are the global signal.
24 . The pixel circuit of claim 22 , wherein the pulse width driving circuit further includes a pulse compensating transistor connected to the control electrode of the pulse driving transistor and a second electrode of the pulse driving transistor, and
wherein the constant current driving circuit further includes a constant current compensating transistor connected to the control electrode of the constant current driving transistor and a second electrode of the constant current driving transistor.
25 . The pixel circuit of claim 24 , wherein the pulse compensating transistor and the constant current compensating transistor are N-type transistors.
26 . An electronic device comprising:
a pixel circuit; and
a power supply configured to provide power to the pixel circuit,
wherein the pixel circuit comprises:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor configured to apply a data voltage to the second node in response to a first scan signal;
a third transistor configured to connect the first node and the third node in response to the first scan signal;
a fourth transistor configured to apply a first power voltage to the second node in response to an emission signal;
a fifth transistor configured to connect the third node and a fourth node in response to the emission signal;
a sixth transistor configured to apply an initialization voltage to the first node in response to a first initialization signal;
a seventh transistor including a control electrode connected to the fourth node, a first electrode connected to a fifth node and a second electrode connected to a sixth node and configured to generate a driving current;
an eighth transistor configured to apply the data voltage to the fifth node in response to a second scan signal;
a tenth transistor configured to apply a second power voltage to the fifth node in response to the emission signal;
a twelfth transistor configured to apply the initialization voltage to the fourth node in response to a second initialization signal; and
a light emitting element configured to emit light based on the driving current,
wherein the first transistor and the seventh transistor are P-type transistors, and the second transistor, the third transistor and the eighth transistor are N-type transistors, and
wherein a sweep signal is applied to the first node, and the sweep signal is a global signal which has a same timing across at least two pixel-rows.