IP Library Granted Patent US 12,688,825
Granted Patent B2
US 12,688,825 · App. 18/539,482 · Granted Jul 21, 2026

Display panel, pixel circuit arranged therein and display device including the same

Inventors: Ki Min Son (Paju-si, KR); Ki Bok Park (Paju-si, KR); Chang Hee Kim (Paju-si, KR)
Assignee: LG Display Co., Ltd.
G09G3/3233G09G3/3266G09G2300/0452G09G2300/0852G09G2300/0861G09G2310/061G09G2310/08
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Quick Facts
Patent No.
US 12,688,825
App. No.
18/539,482
Granted
Jul 21, 2026
Kind
B2
Abstract

Disclosed are a display panel, a pixel circuit arranged therein and a display device including the same. The display panel includes a sub-pixel of a first color, a sub-pixel of a second color, and a sub-pixel of a third color. Each of the sub-pixels of the first color, the second color, and the third color includes: a driving element including a first electrode coupled to a first node, a gate electrode coupled to a second node, and a second electrode coupled to a third node. The display panel includes a light emitting element including an anode electrode connected to the fourth node and configured to be driven by a current from the driving element; a first capacitor connected between the second node and the third node; and a second capacitor coupled between a constant voltage line and the third node or between the third node and the fourth node.

Claims (151)

1 . A display panel, comprising:

a sub-pixel of a first color;

a sub-pixel of a second color; and

a sub-pixel of a third color,

wherein each of the sub-pixels of the first color, the second color, and the third color includes:

a driving element including a first electrode electrically connected to a first node, a gate electrode electrically connected to a second node, and a second electrode electrically connected to a third node; and

a light emitting element including an anode electrode connected to the third node or a fourth node and configured to be driven by a current from the driving element;

a second switch element including a first electrode electrically connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode electrically connected to the fourth node;

a first capacitor electrically connected between the second node and the third node, wherein the first capacitors in the sub-pixels of the first color, the second color, and the third color have a same capacitance; and

a second capacitor electrically connected in parallel with the second switch element between the third node and the fourth node,

wherein the second capacitor has a different capacitance for each of the sub-pixels of the first color, the second color, and the third color,

wherein the second capacitor is electrically connected to a constant voltage line configured to supply a constant voltage,

wherein a capacitance of a capacitor of the light emitting element is increased in an order from larger to smaller of the sub-pixel of the third color, the sub-pixel of the second color, and the sub-pixel of the first color,

wherein the second capacitor includes:

a common electrode extending across the sub-pixels of the first color, the second color, and the third color; and

respective electrodes disposed in the sub-pixels of the first color, the second color, and the third color and having different areas from each other.

2 . The display panel of claim 1 , wherein each of the sub-pixels of the first color, the second color, and the third color further includes:

a first switch element including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a second electrode electrically connected to the first node,

wherein:

the sub-pixel of the first color includes a second-first capacitor;

the sub-pixel of the second color includes a second-second capacitor;

the sub-pixel of the third color includes a second-third capacitor;

the first color is red, the second color is green, and the third color is blue;

a capacitance of the second-third capacitor is larger than a capacitance of each of the second-first capacitor and second-second capacitor; and

the capacitance of the second-second capacitor is larger than the capacitance of the second-first capacitor.

3 . The display panel of claim 2 , further comprising:

a pattern of a first metal layer disposed on a first insulating layer and electrically connected to the sub-pixels of the first color, the second color, and the third color;

a second insulating layer configured to cover the pattern of the first metal layer and the first insulating layer;

patterns of a second metal layer disposed on the second insulating layer, the patterns being arranged on the sub-pixels of the first color, the second color, and the third color and separated among the sub-pixels; and

a third insulating layer configured to cover the patterns of the second metal layer and the second insulating layer, wherein the patterns of the second metal layer includes:

a second-first capacitor electrode disposed in the sub-pixel of the first color;

a second-second capacitor electrode disposed in the sub-pixel of the second color; and

a second-third capacitor electrode disposed in the sub-pixel of the third color, wherein the second-third capacitor electrode is larger than each of the second-first capacitor electrode and second-second capacitor electrode in size; and

the second-second capacitor electrode is larger than the second-first capacitor electrode in size.

4 . The display panel of claim 2 , wherein a constant voltage applied to the second-first capacitor, the second-second capacitor and the second-third capacitor is either equal to or different from the pixel driving voltage.

5 . The display panel of claim 2 , wherein each of the sub-pixels of the first color, the second color, and the third color further includes:

a third switch element including a first electrode electrically connected to a data line to which a data voltage of pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode electrically connected to the second node;

a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode electrically connected to the second node; and

a fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode electrically connected to the fourth node, and

wherein the first capacitors in the sub-pixels of the first color, the second color, and the third color have a same capacitance.

6 . The display panel of claim 5 , wherein a pixel circuit arranged in each of the sub-pixels of the first color, the second color, and the third color is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period;

a voltage of the first gate signal is a gate-on voltage during the initialization period, the sensing period, and the emission period, is a gate-off voltage during the anode reset period, and is the gate-on voltage or the gate-off voltage during the data writing period;

a voltage of the second gate signal is the gate-on voltage during the initialization period, the anode reset period, and the emission period, and is the gate-off voltage during the sensing period and the data writing period;

a voltage of the third gate signal is the gate-on voltage during the data writing period, and is the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the emission period;

a voltage of the fourth gate signal is the gate-on voltage during the initialization period and the sensing period, and is the gate-off voltage during the data writing period, the anode reset period, and the emission period;

a voltage of the fifth gate signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and is the gate-off voltage during the emission period; and

each of the first to fifth switch elements is turned on based on the gate-on voltage, and turned off based on the gate-off voltage.

7 . The display panel of claim 1 , wherein each of the sub-pixels of the first color, the second color, and the third color further includes:

a first switch element including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a second electrode electrically connected to the first node, and

wherein:

the anode electrode of the light emitting element is electrically connected to the third node;

the first color is red, the second color is green, and the third color is blue;

a capacitance of the second-first capacitor is larger than a capacitance of each of the second-second capacitor and second-third capacitor; and

the capacitance of the second-second capacitor is larger than the capacitance of the second-third capacitor.

8 . The display panel of claim 7 , wherein a constant voltage applied to the second-first capacitor, the second-second capacitor and the second-third capacitors is equal to or different from the pixel driving voltage.

9 . The display panel of claim 1 , wherein:

a pixel driving voltage is applied to the first node;

the anode electrode of the light emitting element is electrically connected to the third node;

the first color is red, the second color is green, and the third color is blue;

a capacitance of the second-first capacitor is larger than a capacitance of each of the second-second capacitor and second-third capacitor; and

the capacitance of the second-second capacitor is larger than the capacitance of the second-third capacitor.

10 . The display panel of claim 9 , wherein a constant voltage applied to the second-first capacitor, the second-second capacitor and the second-third capacitor is equal to or different from the pixel driving voltage.

11 . A display device, comprising:

a display panel having a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels;

a data driver configured to output a data voltage of pixel data to the plurality of data lines; and

a gate driver configured to sequentially supply gate signals to the plurality of gate lines, wherein each of the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels includes a pixel circuit, the pixel circuit including:

a driving element including a first electrode electrically connected to a first node to which a pixel driving voltage is applied, a gate electrode electrically connected to a second node, and a second electrode electrically connected to a third node; and

a light emitting element including an anode electrode connected to the third node or a fourth node and configured to be driven by a current from the driving element;

a second switch element including a first electrode electrically connected to the third node, a gate electrode to which a second gate signal is applied, and a second electrode electrically connected to the fourth node;

a first capacitor electrically connected between the second node and the third node; and

a second capacitor electrically connected in parallel with including a first electrode directly connected to the third node and a second electrode connected to the second switch element between the third node and the fourth node, and

wherein the first capacitors in the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels have a same capacitance,

wherein the second capacitor is electrically connected to a constant voltage line configured to supply a constant voltage which is lower than the pixel driving voltage,

wherein a capacitance of the second capacitor is different for each of the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels,

wherein the second capacitor includes:

a common electrode configured to be connected to the constant voltage line and to be extended across the sub-pixels of the first color, the second color, and the third color, and

respective electrodes configured to be connected to the fourth node and be disposed in the sub-pixels of the first color, the second color, and the third color and having different areas from each other.

12 . The display device of claim 11 , wherein each of the sub-pixels further includes:

a first switch element including a first electrode to which a pixel driving voltage is applied, a gate electrode to which a first gate signal is applied, and a second electrode electrically connected to the first node;

a third switch element including a first electrode electrically connected to the data line to which the data voltage of the pixel data is applied, a gate electrode to which a third gate signal is applied, and a second electrode electrically connected to the second node;

a fourth switch element including a first electrode to which an initialization voltage is applied, a gate electrode to which a fourth gate signal is applied, and a second electrode electrically connected to the second node; and

a fifth switch element including a first electrode to which a reference voltage is applied, a gate electrode to which a fifth gate signal is applied, and a second electrode electrically connected to the fourth node, and

wherein:

the constant voltage applied to the second capacitor is equal to or different from the pixel driving voltage;

a capacitance of the first capacitors in the red sub-pixels, the green sub-pixels, and the blue sub-pixels is the same;

the capacitance of the second capacitors in the plurality of blue sub-pixels is larger than the capacitance of each of the second capacitors in the plurality of red and the plurality of green sub-pixels; and

the capacitance of the second capacitors in the plurality of green sub-pixels is larger than the capacitance of the second capacitors in the plurality of red sub-pixels.

13 . The display device of claim 12 , wherein the display panel further includes:

a pattern of a first metal layer disposed on a first insulating layer and electrically connected to the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels;

a second insulating layer configured to cover the pattern of the first metal layer and the first insulating layer;

patterns of a second metal layer disposed on the second insulating layer, the patterns being disposed on the plurality of red sub-pixels, the plurality of green sub-pixels, and the plurality of blue sub-pixels and being separated between neighboring sub-pixels;

a third insulating layer configured to cover the patterns of the second metal layer and the second insulating layer, wherein the patterns of the second metal layer includes:

a second-first capacitor electrode disposed in the plurality of red sub-pixels;

a second-second capacitor electrode disposed in the plurality of green sub-pixels; and

a second-third capacitor electrode disposed in the plurality of blue sub-pixels, wherein the second-third capacitor electrode is larger than each of the second-first capacitor electrode and the second-second capacitor electrode in size; and

the second-second capacitor electrode is larger than the second-first capacitor electrode in size.

14 . A pixel circuit comprising:

a driving element including:

a first electrode electrically connected to a first node to which a pixel driving voltage is applied,

a gate electrode electrically connected to a second node, and

a second electrode electrically connected to a third node;

a light emitting element adjacent to the driving element, the light emitting element including:

a fourth node, and

a cathode electrode to which a cathode voltage is applied;

a second switch element including:

a first electrode electrically connected to the third node,

a gate electrode to which a second emission control signal is applied, and

a second electrode electrically connected to the fourth node, the second switch element configured to electrically connect the third node to the fourth node based on a gate-on voltage of the second emission control signal;

a first capacitor electrically connected between the second node and the third node; and

a second capacitor electrically connected in parallel with including a first electrode directly connected to the third node and a second electrode connected to the second switch element between the third node and the fourth node,

wherein the pixel circuit is included in a sub-pixel of a first color, a sub-pixel of a second color, and a sub-pixel of a third color,

wherein the second capacitor has a different capacitance for each of the sub-pixels of the first color, the second color, and the third color,

wherein the first capacitor has a same capacitance in the sub-pixel of the first color, the sub-pixel of the second color, and the sub-pixel of the third color,

wherein the second capacitor is electrically connected to a constant voltage line configured to supply a constant voltage which is lower than the pixel driving voltage,

wherein a capacitance of a capacitor of the light emitting element is increased in an order from larger to smaller of the sub-pixel of the third color, the sub-pixel of the second color, and the sub-pixel of the first color,

wherein a capacitance of the second capacitor is different for each pixel of different colors,

wherein the second capacitor includes:

a common electrode configured to be connected to the constant voltage line and to be extended across the sub-pixels of the first color, the sub-pixel of the second color, and the sub-pixel of the third color; and

respective electrodes configured to be connected to the fourth node and be disposed in the sub-pixels of the first color, the second color, and the third color and having different areas from each other.

15 . The pixel circuit of claim 14 , further comprising:

a first switch element including:

a first electrode electrically connected to a constant voltage line to which a pixel driving voltage is applied,

a gate electrode to which a first emission control signal is applied, and

a second electrode electrically connected to the first node, the first switch element configured to electrically connect the constant voltage line to the first node based on a gate-on voltage of the first emission control signal;

a third switch element including:

a first electrode to which a data voltage is applied,

a gate electrode to which a first scan signal is applied, and

a second electrode electrically connected to the second node, the third switch element configured to supply the data voltage to the second node based on a gate-on voltage of the first scan signal;

a fourth switch element including:

a first electrode to which an initialization voltage is applied,

a gate electrode to which a second scan signal is applied, and

a second electrode electrically connected to the second node, the fourth switch element configured to supply the initialization voltage to the second node based on a gate-on voltage of the second scan signal;

a fifth switch element including:

a first electrode electrically connected to the fourth node,

a gate electrode to which a third scan signal is applied, and

a second electrode to which a reference voltage is applied, the fifth switch element configured to supply the reference voltage to the fourth node based on a gate-on voltage of the third scan signal.

16 . The pixel circuit of claim 15 , wherein the pixel circuit is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period;

a voltage of the first emission control signal is a gate-on voltage during the initialization period, the sensing period, and the emission period, is a gate-off voltage during the anode reset period, and is the gate-on voltage or the gate-off voltage during the data writing period;

a voltage of the second emission control signal is the gate-on voltage during the initialization period, the anode reset period, and the emission period, and is the gate-off voltage during the sensing period and the data writing period;

a voltage of the first scan signal is the gate-on voltage during the data writing period, and is the gate-off voltage during the initialization period, the sensing period, the anode reset period, and the emission period;

a voltage of the second scan signal is the gate-on voltage during the initialization period and the sensing period, and is the gate-off voltage during the data writing period, the anode reset period, and the emission period;

a voltage of the third scan signal is the gate-on voltage during the initialization period, the sensing period, the data writing period, and the anode reset period, and is the gate-off voltage during the emission period; and

each of the first to fifth switch elements is turned on based on the gate-on voltage and turned off based on the gate-off voltage.

17 . The pixel circuit of claim 15 , wherein the pixel circuit is driven in an order of an initialization period, a sensing period, a data writing period, an anode reset period, and an emission period;

during the initialization period, the initialization voltage is applied to the second node and the reference voltage is applied to the third node;

during the sensing period, a threshold voltage of the driving element is stored in the first capacitor;

during the data writing period, the data voltage is applied to the second node;

during the anode reset period, the reference voltage is applied to the third node and the fourth node; and

during a boosting period of the emission period, the second switch element is turned on so that the third node and the fourth node are electrically connected to each other, and

wherein the light emitting element emits light in accordance with a current from the driving element after the boosting period.

18 . The pixel circuit of claim 17 , wherein during the boosting period, a speed of voltage boosting of the second node and the third node is faster.