Driving circuit including control circuit and output circuit controlled by voltage levels of nodes of the control circuit

1 . A driving circuit comprising a plurality of stages,

wherein each of the plurality of stages comprises:

a first transistor connected between a first node and a first terminal to which a first voltage is input, the first transistor comprising a gate connected to a first input terminal to which a start signal is input;

a second transistor connected between a second node and a second terminal to which a second voltage lower than the first voltage is input, the second transistor comprising a gate connected to the first node;

a third transistor connected between the first terminal and the second node and comprising a gate connected to a second input terminal to which a carry signal is input;

a fourth transistor connected between the first node and the second terminal and comprising a gate connected to the second node; and

an output circuit configured to be controlled by voltage levels of the first node and the second node and output an output signal.

2 . The driving circuit of claim 1 , wherein each of the plurality of stages further comprises a fifth transistor connected between the first terminal and the first node and comprising a gate connected to the second node.

3 . The driving circuit of claim 1 , wherein each of the plurality of stages further comprises a capacitor connected to the first terminal and the first node.

4 . The driving circuit of claim 1 , wherein each of the plurality of stages further comprises a sixth transistor connected between the first terminal and the second node and comprising a gate connected to the first node.

5 . The driving circuit of claim 1 , wherein each of the plurality of stages further comprises a reset transistor connected between the first terminal and the second node and comprising a gate configured to receive a reset signal.

6 . The driving circuit of claim 1 , wherein

each of the second transistor and the fourth transistor comprises a back gate connected to a third terminal to which a third voltage lower than the second voltage is input.

7 . The driving circuit of claim 1 , wherein the output circuit comprises:

a seventh transistor connected between an output terminal and a clock terminal to which a clock signal is input, the seventh transistor comprising a gate connected to a third node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the first node; and

a transfer transistor connected between the second node and the third node and comprising a gate connected to the second terminal.

8 . The driving circuit of claim 7 , wherein the output circuit further comprises a capacitor connected to the output terminal and the third node.

9 . The driving circuit of claim 1 , wherein

the start signal is an output signal output from a previous stage, and

the carry signal is an output signal output from a next stage.

10 . The driving circuit of claim 1 , wherein the output circuit comprises a plurality of sub-output circuits connected in parallel,

wherein each of the plurality of sub-output circuits comprises:

a seventh transistor connected between an output terminal and a clock terminal and comprising a gate connected to a sub-node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the first node; and

a transfer transistor connected between the second node and the sub-node and comprising a gate connected to the second terminal, and

wherein clock signals input to the clock terminals of the plurality of sub-output circuits, respectively, are sequentially shifted signals, and

the output terminals of the plurality of sub-output circuits are configured to sequentially output output signals at intervals corresponding to shift intervals of the clock signals.

11 . The driving circuit of claim 10 , wherein each of the plurality of sub-output circuits further comprises a capacitor connected to the output terminal and the sub-node.

12 . The driving circuit of claim 10 , wherein

the start signal is one of output signals output from a previous stage, and

the carry signal is one of output signals output from a next stage.

13 . The driving circuit of claim 1 , wherein

each of the first transistor and the third transistor is a first conductivity-type transistor, and

each of the second transistor and the fourth transistor is a second conductivity-type transistor.

14 . A driving circuit comprising a plurality of stages,

wherein each of the plurality of stages comprises:

a first transistor connected between a first input terminal, to which a start signal is input, and a first node;

a second transistor connected between a first terminal, to which a first voltage is input, and a second node, the second transistor comprising a gate connected to the first node;

a third transistor connected between the second node and a second terminal, to which a second voltage lower than the first voltage is input, or a third terminal, to which a third voltage lower than the first voltage and higher than the second voltage is input, the third transistor comprising a gate connected to the first node; and

an output circuit configured to be controlled by voltage levels of the first node and the second node and output an output signal,

wherein the third transistor further comprises a back gate connected to a fourth terminal, to which a fourth voltage lower than the second voltage is input, and

wherein a signal input to the gate of the second transistor and the gate of the third transistor is a voltage of the first node.

15 . The driving circuit of claim 14 , wherein each of the plurality of stages further comprises a fourth transistor connected between the first terminal and the first node and comprising a gate connected to a second input terminal to which a carry signal is input, and

wherein a gate of the first transistor is connected to the first input terminal.

16 . The driving circuit of claim 15 , wherein

the start signal is an output signal output from a previous stage, and

the carry signal is an output signal output from a next stage.

17 . The driving circuit of claim 15 , wherein the output circuit comprises:

a seventh transistor connected between an output terminal and a clock terminal to which a clock signal is input, the seventh transistor comprising a gate connected to a third node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the second node; and

a transfer transistor connected between the first node and the third node and comprising a gate connected to the second terminal.

18 . The driving circuit of claim 17 , wherein the output circuit further comprises

a capacitor connected to the output terminal and the third node.

19 . The driving circuit of claim 15 , wherein the output circuit comprises a plurality of sub-output circuits connected in parallel,

wherein each of the plurality of sub-output circuits comprises:

a seventh transistor connected between an output terminal and a clock terminal to which a clock signal is input, the seventh transistor comprising a gate connected to a sub-node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the second node; and

a transfer transistor connected between the first node and the sub-node and comprising a gate connected to the second terminal, and

wherein clock signals input to the clock terminals of the plurality of sub-output circuits, respectively, are sequentially shifted signals, and

the output terminals of the plurality of sub-output circuits are configured to sequentially output output signals at intervals corresponding to shift intervals of the clock signals.

20 . The driving circuit of claim 19 , wherein each of the plurality of sub-output circuits further comprises a capacitor connected to the output terminal and the sub-node.

21 . The driving circuit of claim 20 , wherein

the start signal is one of output signals output from a previous stage, and

the carry signal is one of output signals output from a next stage.

22 . The driving circuit of claim 14 , wherein the output circuit comprises:

a seventh transistor connected between an output terminal and a first clock terminal to which a first clock signal is input, the seventh transistor comprising a gate connected to a third node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the second node; and

a transfer transistor connected between the first node and the third node and comprising a gate connected to the second terminal,

wherein a gate of the first transistor is connected to a second clock terminal to which a second clock signal is input, and the second clock signal is input by shifting the first clock signal.

23 . The driving circuit of claim 22 , wherein the start signal is an output signal output from a previous stage.

24 . The driving circuit of claim 22 , wherein the output circuit further comprises a capacitor connected to the output terminal and the third node.

25 . The driving circuit of claim 14 , wherein the output circuit comprises a plurality of sub-output circuits connected in parallel,

wherein each of the plurality of sub-output circuits comprises:

a seventh transistor connected between an output terminal and a first clock terminal to which a first clock signal is input, the seventh transistor comprising a gate connected to a sub-node;

an eighth transistor connected between the first terminal and the output terminal and comprising a gate connected to the second node; and

a transfer transistor connected between the first node and the sub-node and comprising a gate connected to the second terminal,

wherein a gate of the first transistor is connected to a second clock terminal to which a second clock signal is input,

wherein the second clock signal is a signal shifted from the first clock signal, and

wherein first clock signals input to the first clock terminals of the plurality of sub-output circuits, respectively, are sequentially shifted signals, and

the output terminals of the plurality of sub-output circuits are configured to sequentially output output signals at intervals corresponding to shift intervals of the first clock signals.

26 . The driving circuit of claim 25 , wherein each of the plurality of sub-output circuits further comprises a capacitor connected to the output terminal and the sub-node.

27 . The driving circuit of claim 14 , wherein

each of the first transistor and the second transistor is a first conductivity-type transistor, and

the third transistor is a second conductivity-type transistor.