Pixel circuits for liquid crystal on silicon phase modulator
Disclosed herein is a frame buffer pixel circuit having a first data pass gate transistor G 1 , first storage capacitor C 1 , a voltage boosting line Vb, source follower transistor F, pull-down transistor P, and second data pass gate transistor G 2 . The pull-down transistor P is connected to the drain of transistor F and source of transistor G 2 and the storage capacitor C 1 is connected to a voltage boosting line Vb. In the operation, Vb is set to zero volt when data is transferring to Cl capacitor through G 1 gate. After the frame data are loaded onto C 1 capacitors in all pixels, Vb is set to designed voltage and G 2 gates in all pixels are opened to charge Clcd capacitors. Vb is then set to zero volt again before starting to load next frame data onto pixels. Such process is iterated in the liquid crystal on silicon (LCOS) working time.
1 . A circuit of controlling a pixel electrode of a liquid crystal on silicon backplane phase modulator, comprising:
two data transfer controllers;
a data storage capacitor;
a voltage booster directly connected to the data storage capacitor; and
a source follower transistor in series with a pull-down unit transistor,
wherein the circuit is configured to first transfer an analog data signal through first data transfer controller and is configured to store at the data storage capacitor; and
wherein the voltage booster is configured to switch from zero volts to a desired voltage and is configured to then transfer the data through the second controller to a liquid crystal driving electrode.
2 . The circuit of claim 1 , wherein the pull-down transistor is positioned before the second data transfer controller.
3 . The circuit of claim 1 , wherein transistors in the circuit are all NMOS transistors.
4 . The circuit of claim 1 , wherein the data storage capacitor is connected to a gate transistor that can provide 0V or a desired boosting voltage.
5 . A system for controlling a pixel electrode of a liquid crystal on silicon backplane phase modulator, the system comprising:
a first data transfer controller and a second data transfer controller,
one data storage capacitor,
a voltage booster directly connected to the data storage capacitor, and
a source follower transistor in series with a pull-down transistor,
wherein the voltage booster is configured to switch from zero volts to a predetermined voltage and is configured to then transfer the data through the second data transfer controller to a liquid crystal driving electrode.
6 . The system of claim 5 , wherein an analog data signal is first transferred through the first data transfer controller and stored at the storage capacitor.
7 . The system of claim 5 , wherein further comprising the pull-down transistor positioned before the second data transfer controller.
8 . The system of claim 5 , wherein each transistor in the system is an NMOS transistor.
9 . The system of claim 5 , further comprising a data storage capacitor connected to a gate transistor that can provide 0V or a predetermined boosting voltage.