IP Library › Granted Patent US 12688881

Granted Patent B2

US 12688881 · App. 18/349,013 · Granted Jul 21, 2026

Thyristor memory cell, thyristor memory array, and method for fabricating a thyristor memory array

Inventors: Sheng-Chih Lai (Hsinchu, TW); Chen-Jun Wu (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

G11C11/39 H10B99/20 H10D18/40 H10D62/822 H10D62/824 H10D84/0102 H10D84/60

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Quick Facts

Patent No.: US 12688881
App. No.: 18/349,013
Granted: Jul 21, 2026
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A thyristor memory cell includes a semiconductor cathode, a first un-doped semiconductor feature connected to the semiconductor cathode, a second un-doped semiconductor feature connected to the first un-doped semiconductor feature, a semiconductor anode connected to the second un-doped semiconductor feature, and a gate feature disposed on the first un-doped semiconductor feature or the second un-doped semiconductor feature. Among the semiconductor cathode, the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor anode, the semiconductor anode has the highest bottom edge of conduction band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order; and the semiconductor anode has the highest top edge of the valence band, followed by the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor cathode in the given order.

Claims (68)

1 . A thyristor memory cell, comprising:

a semiconductor cathode;

a first un-doped semiconductor feature that is connected to the semiconductor cathode;

a second un-doped semiconductor feature that is connected to the first un-doped semiconductor feature;

a semiconductor anode that is connected to the second un-doped semiconductor feature; and

a gate feature that is disposed on one of the first un-doped semiconductor feature and the second un-doped semiconductor feature;

wherein a bottom edge of a conduction band of the semiconductor anode is higher than a bottom edge of a conduction band of the first un-doped semiconductor feature, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor feature, which is higher than a bottom edge of a conduction band of the semiconductor cathode;

wherein a top edge of a valence band of the semiconductor anode is higher than a top edge of a valence band of the first un-doped semiconductor feature, which is higher than a top edge of a valence band of the second un-doped semiconductor feature, which is higher than a top edge of a valence band of the semiconductor cathode; and

wherein the gate feature surrounds the one of the first un-doped semiconductor feature and the second un-doped semiconductor feature.

2 . The thyristor memory cell according to claim 1 , wherein one of the semiconductor anode and the semiconductor cathode is spaced apart from a semiconductor substrate.

3 . The thyristor memory cell according to claim 2 , wherein the semiconductor cathode, the first un-doped semiconductor feature, the second un-doped semiconductor feature and the semiconductor anode are stacked together in a direction perpendicular to a surface of the semiconductor substrate.

4 . The thyristor memory cell according to claim 1 , wherein the semiconductor cathode is made of an N-doped material whose base material is same as a material that forms the second un-doped semiconductor feature.

5 . The thyristor memory cell according to claim 4 , wherein the semiconductor anode is made of a P-doped material whose base material is a group III-V semiconductor, which is same as a material that forms the first un-doped semiconductor feature.

6 . The thyristor memory cell according to claim 1 , wherein the semiconductor anode is made of a P-doped material whose base material is a group III-V semiconductor, which is same as a material that forms the first un-doped semiconductor feature.

7 . The thyristor memory cell according to claim 1 , wherein the semiconductor cathode is made of an N-doped material whose base material is Si, the first un-doped semiconductor feature is made of SiGe, the second un-doped semiconductor feature is made of Si, and the semiconductor anode is made of a P-doped material whose base material is SiGe.

8 . The thyristor memory cell according to claim 1 , wherein the first un-doped semiconductor feature and the second un-doped semiconductor feature are made of different group III-V semiconductors.

9 . The thyristor memory cell according to claim 1 , wherein the semiconductor cathode is made of an N-doped material whose base material is InAs, the first un-doped semiconductor feature is made of InAsSb, the second un-doped semiconductor feature is made of InAs, and the semiconductor anode is made of a P-doped material whose base material is InAsSb.

10 . The thyristor memory cell according to claim 1 , wherein the semiconductor cathode is made of an N-doped material whose base material is InP, the first un-doped semiconductor feature is made of GaAsSb, the second un-doped semiconductor feature is made of InP, and the semiconductor anode is made of a P-doped material whose base material is GaAsSb.

11 . The thyristor memory cell according to claim 1 , wherein the gate feature surrounds the second un-doped semiconductor feature.

12 . A thyristor memory array, comprising:

a plurality of first thyristor memory cells arranged in a first array that includes multiple columns and multiple rows, wherein the columns are arranged in a first direction, and the rows are arranged in a second direction that is perpendicular to the first direction; and

a plurality of second thyristor memory cells arranged in a second array that is stacked over the first array and that includes multiple columns and multiple rows, wherein the columns of the second array are arranged in the first direction, and the rows of the second array are arranged in the second direction;

wherein each of the first thyristor memory cells includes:

a semiconductor cathode;

a first un-doped semiconductor feature that is stacked on the semiconductor cathode in a third direction which is perpendicular to the first direction and the second direction;

a second un-doped semiconductor feature that is stacked on the first un-doped semiconductor feature in the third direction;

a semiconductor anode that is stacked on the second un-doped semiconductor feature in the third direction; and

a gate feature that is disposed on one of the first un-doped semiconductor feature and the second un-doped semiconductor feature;

wherein each of the second thyristor memory cells includes a semiconductor anode, a first un-doped semiconductor feature, a second un-doped semiconductor feature, a semiconductor cathode and a gate feature;

wherein, for each of the second thyristor memory cells:

the second un-doped semiconductor feature of the second thyristor memory cell is stacked on the semiconductor anode of the second thyristor memory cell in the third direction;

the first un-doped semiconductor feature of the second thyristor memory cell is stacked on the second un-doped semiconductor feature of the second thyristor memory cell in the third direction;

the semiconductor cathode of the second thyristor memory cell is stacked on the first un-doped semiconductor feature of the second thyristor memory cell in the third direction; and

the gate feature of the second thyristor memory cell is disposed on one of the first un-doped semiconductor feature and the second un-doped semiconductor feature of the second thyristor memory cell;

wherein a bottom edge of a conduction band of the semiconductor anode of the second thyristor memory cell is higher than a bottom edge of a conduction band of the first un-doped semiconductor feature of the second thyristor memory cell, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor feature of the second thyristor memory cell, which is higher than a bottom edge of a conduction band of the semiconductor cathode of the second thyristor memory cell; and

wherein a top edge of a valence band of the semiconductor anode of the second thyristor memory cell is higher than a top edge of a valence band of the first un-doped semiconductor feature of the second thyristor memory cell, which is higher than a top edge of a valence band of the second un-doped semiconductor feature of the second thyristor memory cell, which is higher than a top edge of a valence band of the semiconductor cathode of the second thyristor memory cell.

13 . The thyristor memory array according to claim 12 , further comprising a plurality of bit lines that extend in the first direction and that respectively correspond to the rows of the first array;

wherein each of the bit lines is electrically connected to the semiconductor anodes of those of the first thyristor memory cells that are in the corresponding one of the rows.

14 . The thyristor memory array according to claim 13 , wherein, for each of the columns, the gate features of the first thyristor memory cells in the column are electrically connected to each other; and

wherein the semiconductor cathodes of the first thyristor memory cells are electrically connected together.

15 . The thyristor memory array according to claim 12 , wherein the first un-doped semiconductor feature of the first thyristor memory cell and the first un-doped semiconductor feature of the second thyristor memory cell are made of a same material; and

wherein the second un-doped semiconductor feature of the first thyristor memory cell and the second un-doped semiconductor feature of the second thyristor memory cell are made of a same material.

16 . The thyristor memory array according to claim 13 , wherein the rows of the second array respectively correspond to the bit lines; and

wherein each of the bit lines is electrically connected to the semiconductor anodes of those of the second thyristor memory cells that are in the corresponding one of the rows of the second array.

17 . A method for fabricating a thyristor memory array, comprising steps of:

forming a first stack feature that includes a first semiconductor layer, a first dielectric layer over the first semiconductor layer, a first sacrificial layer over the first semiconductor layer, and a second dielectric layer stacked over the first sacrificial layer and the first dielectric layer;

forming a plurality of first holes in the first stack feature, the first holes being arranged in a first array that includes multiple columns and multiple rows, and penetrating through the second dielectric layer, the first sacrificial layer and the first dielectric layer, wherein the columns are arranged in a first direction, and the rows are arranged in a second direction that is perpendicular to the first direction;

forming a plurality of first semiconductor stacks respectively in the first holes, each of the first semiconductor stacks including a first un-doped semiconductor layer stacked on the first semiconductor layer, a second un-doped semiconductor layer stacked on the first un-doped semiconductor layer, and a second semiconductor layer stacked on the second un-doped semiconductor layer;

forming a plurality of first slits in the first stack feature, each of the first slits being arranged in the first direction, extending in the second direction, penetrating through at least the second dielectric layer and the first sacrificial layer, and being disposed between adjacent two of the columns of the first array;

removing the first sacrificial layer through the first slits to partly expose the first semiconductor stacks; and

forming a first gate feature on each of the first semiconductor stacks through the first slits;

wherein a bottom edge of a conduction band of the second semiconductor layer is higher than a bottom edge of a conduction band of the first un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the second un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the first semiconductor layer; and

wherein a top edge of a valence band of the second semiconductor layer is higher than a top edge of a valence band of the first un-doped semiconductor layer, which is higher than a top edge of a valence band of the second un-doped semiconductor layer, which is higher than a top edge of a valence band of the first semiconductor layer.

18 . The method according to claim 17 , further comprising a step of:

forming a plurality of bit lines over the second dielectric layer and the second semiconductor layers of the first semiconductor stacks;

wherein the bit lines extend in the first direction and respectively correspond to the rows of the first array; and

wherein each of the bit lines is electrically connected to the second semiconductor layers of some of the first semiconductor stacks that are formed in those of the first holes in the corresponding one of the rows of the first array.

19 . The method according to claim 18 , further comprising steps of:

forming a second stack feature over the bit lines, the second stack feature including multiple dielectric layers;

forming a plurality of second semiconductor stacks in the second stack feature, the second semiconductor stacks being arranged in a second array that includes multiple columns and multiple rows, each of the second semiconductor stacks penetrating through the second stack feature, and including a third semiconductor layer formed on one of the bit lines, a third un-doped semiconductor layer over the third semiconductor layer, and a fourth un-doped semiconductor layer stacked on the third un-doped semiconductor layer, wherein the columns of the second array are arranged in the first direction, and the rows of the second array are arranged in the second direction and respectively correspond to the bit lines;

forming a second gate feature on each of the second semiconductor stacks; and

forming a fourth semiconductor layer over the second stack feature and the fourth un-doped semiconductor layers of the second semiconductor stacks;

wherein a bottom edge of a conduction band of the third semiconductor layer is higher than a bottom edge of a conduction band of the fourth un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the third un-doped semiconductor layer, which is higher than a bottom edge of a conduction band of the fourth semiconductor layer; and

wherein a top edge of a valence band of the third semiconductor layer is higher than a top edge of a valence band of the fourth un-doped semiconductor layer, which is higher than a top edge of a valence band of the third un-doped semiconductor layer, which is higher than a top edge of a valence band of the fourth semiconductor layer.

20 . The method according to claim 19 , wherein the second un-doped semiconductor layers of the first semiconductor stacks and the third un-doped semiconductor layers of the second semiconductor stacks are made of a same material; and

wherein the first un-doped semiconductor layers of the first semiconductor stacks and the fourth un-doped semiconductor layers of the second semiconductor stacks are made of a same material.