Programming for non-volatile memory

1 . A circuit for generating adaptive SET pulse currents for phase-change memory (PCM) cells, the circuit comprising:

a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current with a programmable profile, the programmable profile comprising:

a constant current phase at a predefined set current,

a first ramping-down phase from the predefined set current to a minimum cutoff current,

a second ramping-down phase from the minimum cutoff current to zero, and

a zero-current phase, wherein the constant current phase for each IDAC starts in response to the other IDAC starting the second ramping-down phase; and

a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate the adaptive SET pulse currents.

2 . The circuit of claim 1 , wherein the programming circuit is configured to:

current scale the selected bias current based on a predetermined multiplier to generate a scaled bias current; and

apply the scaled bias current to a subset of the PCM cells.

3 . The circuit of claim 1 , wherein the programming circuit is configured to generate a first SET pulse current for programming a first PCM cell and a second SET pulse current for programming a second PCM cell.

4 . The circuit of claim 1 , wherein the programming circuit is configured to generate a first SET pulse current and a second SET pulse current with overlapping non-zero current values during a time interval, and wherein the overlapping non-zero current values enable simultaneous programming of a first plurality of PCM cells and a second plurality of PCM cells.

5 . The circuit of claim 4 , wherein a sum of the overlapping non-zero current values equals a maximum current value provided by a charge pump configured for writing to PCM cells.

6 . The circuit of claim 1 , wherein the programming circuit comprises:

a plurality of switches configured to select the bias current from the first IDAC and the second IDAC; and

a current mirror configured to current scale the selected bias current based on a predetermined multiplier to generate a scaled bias current.

7 . The circuit of claim 1 , further comprising a controller coupled to the first IDAC, the second IDAC, and the programming circuit, the controller configured to control a timing of a first SET pulse current for programming a first PCM cell and a second SET pulse current for programming a second PCM cell.

8 . A circuit for generating adaptive SET pulse currents for phase-change memory (PCM) cells, the circuit comprising:

a first subcircuit configured to generate a fixed current;

a second subcircuit configured to generate a continuously adjustable fixed current;

a third subcircuit configured to generate a dynamically adjustable current; and

a pair of current digital-to-analog converters (IDACs), each IDAC comprising:

a plurality of first transistors controlled by the fixed current,

a second transistor controlled by the continuously adjustable fixed current,

a third transistor controlled by the dynamically adjustable current,

a plurality of fourth transistors, each coupled to one of the first transistors, second transistor, and third transistor and controlled by an associated enable signal,

a common summing node coupled to a drain terminal of each fourth transistor,

a diode-connected transistor configured to generate a bias current with a programmable profile based on a summed current at the common summing node, and

a current mirror configured to replicate the summed current at the common summing node at a drain terminal of the diode-connected transistor.

9 . The circuit of claim 8 , further comprising a programming circuit configured to select a bias current from each IDAC and generate the adaptive SET pulse currents.

10 . The circuit of claim 9 , wherein the programming circuit is configured to:

current scale the selected bias current based on a predetermined multiplier to generate a scaled bias current; and

apply the scaled bias current to a subset of the PCM cells.

11 . The circuit of claim 9 , wherein the programming circuit is configured to generate a first SET pulse current for programming a first PCM cell and a second SET pulse current for programming a second PCM cell.

12 . The circuit of claim 9 , wherein the programming circuit is configured to generate a first SET pulse current and a second SET pulse current with overlapping non-zero current values during a time interval, and wherein the overlapping non-zero current values enable simultaneous programming of a first plurality of PCM cells and a second plurality of PCM cells.

13 . The circuit of claim 12 , further comprising a controller configured to:

generate the enable signals to produce a desired current profile;

selectively enable the third transistor; and

coordinate an operation of each IDAC to generate the first SET pulse current and the second SET pulse current with the overlapping non-zero current values.

14 . The circuit of claim 8 , wherein the programmable profile comprises:

a constant current phase at a predefined set current;

a first ramping-down phase from the predefined set current to a minimum cutoff current;

a second ramping-down phase from the minimum cutoff current to zero; and

a zero-current phase, wherein the constant current phase for each IDAC starts in response to the other IDAC starting the second ramping-down phase.

15 . The circuit of claim 8 , wherein the dynamically adjustable current is a linearly downward ramping current.

16 . A digital-to-analog converter (IDAC), comprising:

a plurality of first transistors controlled by a fixed current;

a second transistor controlled by a continuously adjustable fixed current;

a third transistor controlled by a dynamically adjustable current;

a plurality of fourth transistors, each coupled to one of the first transistors, second transistor, and third transistor and controlled by an associated enable signal;

a common summing node coupled to a drain terminal of each fourth transistor;

a diode-connected transistor configured to generate a bias current with a programmable profile based on a summed current at the common summing node; and

a current mirror configured to replicate the summed current at the common summing node at a drain terminal of the diode-connected transistor.

17 . The IDAC of claim 16 , wherein the IDAC is couplable to a controller configured to generate the enable signals to coordinate an operation of the IDAC for generating the bias current.

18 . The IDAC of claim 16 , wherein the programmable profile comprises:

a constant current phase at a predefined set current;

a first ramping-down phase from the predefined set current to a minimum cutoff current;

a second ramping-down phase from the minimum cutoff current to zero; and

a zero-current phase.

19 . The IDAC of claim 16 , wherein the IDAC is couplable to a programming circuit configured to receive the bias current and generate an adaptive SET pulse current for phase-change memory (PCM) cells based on the bias current.

20 . The IDAC of claim 16 , further comprising:

a plurality of fifth transistors controlled by the fixed current;

a sixth transistor controlled by the continuously adjustable fixed current;

a seventh transistor controlled by the dynamically adjustable current;

a plurality of eighth transistors, each coupled to one of the fifth transistors, sixth transistor, and seventh transistor and controlled by an associated second enable signal;

a second common summing node coupled to a drain terminal of each eighth transistor;

a second diode-connected transistor configured to generate a second bias current with the programmable profile based on a second summed current at the second common summing node; and

a second current mirror configured to replicate the second summed current at the second common summing node at a drain terminal of the second diode-connected transistor.