Sensing time adjustment for program operation in a memory device

1 . A method comprising:

receiving a request to perform a program operation on a set of vertically stacked memory cells of a memory device, wherein each memory cell of the set of vertically stacked memory cells is addressable by a respective wordline;

determining whether at least one memory cell of the set of vertically stacked memory cells is non-programmable due to degradation;

responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable due to degradation, determining, based on a logical state of remaining memory cells of the set of vertically stacked memory cells that are programmable and a number of program erase cycles (PECs) associated with the memory device, a sensing time adjustment value;

adjusting a default sensing time by the sensing time adjustment value to generate an adjusted sensing time associated with a program verify phase of a program operation; and

performing, using the adjusted sensing time, the program operation on the set of vertically stacked memory cells.

2 . The method of claim 1 , wherein determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable comprises:

identifying whether a wordline associated with the at least one memory cell of the set of vertically stacked memory cells is defective.

3 . The method of claim 1 , wherein performing the program operation comprises:

applying, during the program verify phase, the adjusted sensing time.

4 . The method of claim 1 , wherein determining the sensing time adjustment value further comprises:

for a given memory cell of the set of vertically stacked memory cells, identifying, from a plurality of entries in a sensing time adjustment data structure, an entry associated with a programming level of the given memory cell and the number of PECs, the entry comprising the sensing time adjustment value, wherein each entry of the plurality of entries comprises a respective sensing time adjustment value associated with a different programming level and a respective number of PECs.

5 . The method of claim 1 , wherein the set of vertically stacked memory cells is a block of the memory device.

6 . The method of claim 1 , wherein the at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at a top of the set of vertically stacked memory cells.

7 . The method of claim 1 , further comprising:

performing a read operation on the set of vertically stacked memory cells.

8 . The method of claim 1 , further comprising:

responsive to determining that each memory cell of the set of vertically stacked memory cells is programmable, performing, using a default sensing time, the program operation on the set of vertically stacked memory cells.

9 . A system comprising:

a memory device; and

a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:

receiving a request to perform a program operation on a set of vertically stacked memory cells of the memory device, wherein each memory cell of the set of vertically stacked memory cells is addressable by a respective wordline;

determining whether at least one memory cell of the set of vertically stacked memory cells is non-programmable due to degradation;

responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable, determining, based on a logical state of remaining memory cells of the set of vertically stacked memory cells that are programmable and a number of program erase cycles (PECs) associated with the memory device, a sensing time adjustment value;

adjusting a default sensing time by the sensing time adjustment value to generate an adjusted sensing time associated with a program verify phase of a program operation; and

performing, using the adjusted sensing time, the program operation on the set of vertically stacked memory cells.

10 . The system of claim 9 , wherein determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable comprises:

identifying whether a wordline associated with the at least one memory cell of the set of vertically stacked memory cells is defective.

11 . The system of claim 9 , wherein performing the program operation comprises:

applying, during the program verify phase, the adjusted sensing time.

12 . The system of claim 9 , wherein determining the sensing time adjustment value further comprises:

for a given memory cell of the set of vertically stacked memory cells, identifying, from a plurality of entries in a sensing time adjustment data structure, an entry associated with a programming level of the given memory cell and the number of PECs, the entry comprising the sensing time adjustment value, wherein each entry of the plurality of entries comprises a respective sensing time adjustment value associated with a different programming level and a respective number of PECs.

13 . The system of claim 9 , wherein the set of vertically stacked memory cells is a block of the memory device.

14 . The system of claim 9 , wherein the at least one memory cell of the set of vertically stacked memory cells that is non-programmable is a memory cell at a top of the set of vertically stacked memory cells.

15 . The system of claim 9 , wherein the processing device is to perform further operations comprising:

performing a read operation on the set of vertically stacked memory cells.

16 . The system of claim 9 , wherein the processing device is to perform further operations comprising:

responsive to determining that each memory cell of the set of vertically stacked memory cells is programmable, performing, using a default sensing time, the program operation on the set of vertically stacked memory cells.

17 . A non-transitory computer readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

receiving a request to perform a program operation on a first block of a memory device, wherein the first block includes a non-programmable top deck due to degradation of at least one memory cell of a top deck of the first block and a programmable bottom deck; and

performing, using an adjusted sensing time, the program operation on the first block, wherein the adjusted sensing time is determined based on a logical state of a given memory cell of the programmable bottom deck and a number of program erase cycles (PECs) of the memory device.

18 . The non-transitory computer readable storage medium of claim 17 , wherein performing the program operations comprises:

determining the number of program erase cycles (PECs) of the memory device; and

for the given memory cell of the first block, identifying, from a plurality of entries in a sensing time adjustment data structure, an entry associated with a programming level of the given memory cell and the number of PECs, the entry comprising a sensing time adjustment value, wherein each entry of the plurality of entries comprises a respective sensing time adjustment value associated with a different programming level and a respective number of PECs.

19 . The non-transitory computer readable storage medium of claim 17 , wherein the instructions cause the processing device to perform operations further comprising:

responsive to receiving a request to perform a read operation on the first block, performing a read operation on the first block.

20 . The non-transitory computer readable storage medium of claim 17 , wherein the instructions cause the processing device to perform operations further comprising:

receiving a request to perform a program operation on a second block of the memory device, wherein the second block includes a programmable top deck and a programmable bottom deck; and

performing, using a default sensing time, the program operation on the second block.