Method of optimizing erasure and programming pass voltage
Provided is a method of optimizing pass voltage including: determining a sweet point of an initial pass voltage; monitoring a pulse number of ISPP; obtaining a shift of a low boundary value of the pass voltage by a shift of the pulse number of the ISPP at different cycles; monitoring a pulse number of ISPE; obtaining a shift of a high boundary value of the pass voltage by a shift of the pulse number of the ISPE at the different cycles; adding the shift of the high boundary value and the shift of the low boundary value and dividing by 2 to get a shift of the sweet point of the pass voltage; and adding the sweet point of the initial pass voltage and the shift of the sweet point of the pass voltage to obtain an optimized pass voltage value.
1 . A method of optimizing a pass voltage of a memory device, wherein the method is performed by a processor, and when performing the method, the processor is configured to:
determining a sweet point of an initial pass voltage under no pulse programming/pulse erase operations;
monitoring a pulse number of incremental step pulse programming (ISPP);
obtaining a shift of a low boundary value of the pass voltage by a shift of the pulse number of the ISPP at different cycles;
monitoring a pulse number of incremental step pulse erase (ISPE);
obtaining a shift of a high boundary value of the pass voltage by a shift of the pulse number of the ISPE at the different cycles;
adding the shift of the high boundary value and the shift of the low boundary value and dividing by 2 to get a shift of a sweet point of the pass voltage; and
adding the sweet point of the initial pass voltage and the shift of the sweet point of the pass voltage to obtain an optimized pass voltage value, wherein the optimized pass voltage is continuously located between the high boundary value and the low boundary value that converge as a cycle count increases, and a fail bit count of the memory device is reduced by using the optimized pass voltage.
2 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein obtaining the shift of the low boundary value of the pass voltage by the shift of the pulse number of the ISPP at the different cycles comprises:
monitoring a first pulse number X1 of the ISPP at a first cycle;
monitoring a second pulse number X2 of the ISPP at a second cycle; and
putting the first pulse number X1 and the second pulse number X2 into an equation (1) to calculate the shift of the low boundary of the pass voltage,
Y
1
=
-
a
(
X
2
-
X
1
)
(
1
)
wherein Y1 is the shift of the low boundary of the pass voltage, and a is a constant greater than zero.
3 . The method of optimizing the pass voltage of the memory device according to claim 2 , wherein a is greater than zero and less than 1.
4 . The method of optimizing the pass voltage of the memory device according to claim 2 , wherein a is between 0.2 and 0.5.
5 . The method of optimizing the pass voltage of the memory device according to claim 2 , wherein a is between 0.35 and 0.36.
6 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein obtaining the shift of the high boundary value of the pass voltage by the shift of the pulse number of the ISPE at the different cycles comprises:
monitoring a third pulse number X3 of the ISPE at a first cycle;
monitoring a fourth pulse number X4 of the ISPP at a second cycle; and
putting the third pulse number X3 and the fourth pulse number X4 into an equation (2) to calculate the shift of the high boundary value of the pass voltage,
Y
2
=
-
b
(
X
4
-
X
3
)
(
2
)
wherein Y2 is the shift of the high boundary value of the pass voltage, and b is a constant greater than zero.
7 . The method of optimizing the pass voltage of the memory device according to claim 6 , wherein b is greater than zero and less than 1.
8 . The method of optimizing the pass voltage of the memory device according to claim 6 , wherein b is between 0.1 and 0.4.
9 . The method of optimizing the pass voltage of the memory device according to claim 6 , wherein b is between 0.17 and 0.18.
10 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the pulse number the ISPP decreases as a cycle count increases.
11 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the low boundary value of the pass voltage increases as a cycle count increases.
12 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the pulse number of the ISPP is inversely proportional to the low boundary value of the pass voltage as a cycle count changes.
13 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the pulse number of the ISPE increases as a cycle count increases.
14 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the high boundary value of the pass voltage decreases as a cycle count increases.
15 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the pulse number of the ISPE is inversely proportional to the high boundary value of the pass voltage as a cycle count changes.
16 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the high boundary value and low boundary value of the pass voltage converges as a cycle count increases.
17 . The method of optimizing the pass voltage of the memory device according to claim 16 , wherein the optimized pass voltage value converges between the high boundary value and the low boundary value as the cycle count increases.
18 . The method of optimizing the pass voltage of the memory device according to claim 1 , wherein the method is suitable for a NAND flash memory.