Deck reset read
A storage device includes a storage array having multiple decks of NAND cells in a three dimensional (3D) stack. There can be any number of decks that have multiple wordlines in vertical stacks. The decks include a first deck and a second deck. Bias circuitry can apply different voltages to different decks of the storage array. The bias circuitry can apply a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously apply a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck.
1 . A storage device, comprising:
a plurality of decks of three dimensional (3D) NAND cells, the plurality of decks including a first deck and a second deck, each of the plurality of decks having a plurality of wordlines stacked vertically and a pillar;
bias circuitry coupled to the plurality of decks of 3D NAND cells, wherein the bias circuitry is configured to provide a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously provide a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck; and
a read controller coupled to the plurality of decks, wherein the read controller is configured to access the plurality of decks via respective logic and apply a deck reset read pulse following one or more operations that cause carrier accumulation in pillars of the plurality of decks, applying the deck reset read pulse further including simultaneously applying the low bias on the wordlines of the first deck to keep holes in the pillar of the first deck and applying the high bias on the wordlines of the second deck to introduce electrons to the pillar of the second deck.
2 . The storage device of claim 1 , wherein the bias circuitry is to apply the low bias to the first deck and the high bias to the second deck based on timing.
3 . The storage device of claim 1 , wherein the read controller is configured to apply the deck reset read pulse after applying a weak erase pulse (WEP) controlling the storage device to inject holes into the plurality of decks.
4 . The storage device of claim 1 , wherein the read controller is configured to apply the deck reset read pulse after bringing the storage device up from a suspend state.
5 . The storage device of claim 1 , wherein the read controller is configured to apply the deck reset read pulse after bringing the storage device up from an idle state.
6 . The storage device of claim 1 , wherein the bias circuitry is to apply the low bias to the first deck to select the first deck for the holes including first excess pillar holes, and is to apply the high bias to the second deck to deselect the second deck from having second excess pillar holes.
7 . The storage device of claim 6 , wherein selection and deselection are based on a storage policy for the storage device.
8 . The storage device of claim 6 , wherein selection and deselection are based on a temperature of the storage device.
9 . The storage device of claim 6 , wherein selection and deselection are based on an architecture of the 3D NAND cells.
10 . A system comprising:
a processor device; and
a storage device coupled to the processor device, the storage device including:
a plurality of decks of three dimensional (3D) NAND cells, the plurality of decks including a first deck and a second deck, each of the plurality of decks having a plurality of wordlines stacked vertically and a pillar;
bias circuitry coupled to the plurality of decks of 3D NAND cells, wherein the bias circuitry is configured to provide a low bias to the first deck, with a first voltage low enough to not turn on the NAND cells of the first deck, and simultaneously provide a high bias to the second deck, with a second voltage high enough to turn on the NAND cells of the second deck; and
a read controller coupled to the plurality of decks, wherein the read controller is configured to access the plurality of decks via respective logic and apply a deck reset read pulse following one or more operations that cause carrier accumulation in pillars of the plurality of decks, applying the deck reset read pulse further including simultaneously applying the low bias on the wordlines of the first deck to keep holes in the pillar of the first deck and applying the high bias on the wordlines of the second deck to introduce electrons to the pillar of the second deck.
11 . The system of claim 10 , wherein the bias circuitry is to apply the low bias to the first deck and the high bias to the second deck based on timing.
12 . The system of claim 10 , wherein the read controller is configured to apply the deck reset read pulse after applying a weak erase pulse (WEP) controlling the storage device to inject holes into the plurality of decks.
13 . The system of claim 10 , wherein the read controller is configured to apply the deck reset read pulse after bringing the storage device up from one of a suspend state and an idle state.
14 . The system of claim 10 , wherein the bias circuitry is to apply the low bias to the first deck to select the first deck for the holes including first excess pillar holes, and is to apply the high bias to the second deck to deselect the second deck from having second excess pillar holes.
15 . The system of claim 14 , wherein selecting the first deck and deselecting the second deck are based on at least one of a storage policy for the storage device, a temperature of the storage device, or an architecture of the 3D NAND cells.
16 . The system of claim 10 , wherein the processor device comprises a multicore processor, and the system further comprises one or more of:
a display communicatively coupled to the processor device;
a battery configured to power the system; and
a network interface circuit to be coupled to a remote device over a network connection.
17 . A method implemented at a storage device, comprising:
simultaneously providing a low bias for a first deck of the storage device and providing a high bias to a second deck of the storage device, wherein:
the storage device includes a plurality of decks further including the first deck and the second deck;
each of the plurality of decks includes three dimensional (3D) NAND cells, a plurality of wordlines stacked vertically, and a pillar; and
the low bias includes a first voltage low enough to not turn on the NAND cells of the first deck, and the high bias includes a second voltage high enough to turn on the NAND cells of the second deck;
accessing the plurality of decks to apply a deck reset read pulse following one or more operations that cause carrier accumulation in pillars of the plurality of decks; and
applying the deck reset read pulse, including simultaneously applying the low bias on the wordlines of the first deck to keep holes in the pillar of the first deck and applying the high bias on the wordlines of the second deck to introduce electrons to the pillar of the second deck.
18 . The method of claim 17 , wherein accessing the plurality of decks further comprises:
selecting the first deck for the holes including first excess pillar holes; and
deselecting the second deck from having second excess pillar holes.
19 . The method of claim 18 , wherein selecting the first deck and deselecting the second deck are based on at least one of a storage policy for the storage device, a temperature of the storage device, or an architecture of the 3D NAND cells.
20 . The method of claim 17 , wherein the deck reset read pulse is applied after a weak erase pulse (WEP) is applied to inject holes into the plurality of decks, after the storage device up is brought up from a suspend state, after the storage device is brought up from an idle state.