Semiconductor device and testing method for memory circuit

1 . A semiconductor device comprising an SRAM (Static Random Access Memory) circuit operating based on an external power supply voltage,

wherein the SRAM circuit includes:

a memory cell array in which a plurality of memory cells including the first memory cell are arranged in a matrix form including a plurality of rows and a plurality of columns;

a first bit line pair extending in a first direction;

a column decoder configured to decode a column address and to select a column corresponding to the decoded column address;

a first word line extending in a second direction intersecting with the first direction;

a row decoder configured to decode a row address and to select a row corresponding to the decoded row address;

a first word line driver driving the first word line;

a first memory cell electrically connected to the first bit line pair and the first word line, wherein the first word line corresponds to one of the plurality of rows, and the first bit line pair corresponds to one of the plurality of columns;

a first power supply line supplying an operating voltage to the first memory cell;

a power supply voltage reduction circuit generating a reduction voltage obtained by lowering the external power supply voltage, and outputting the reduction voltage to a voltage supply line;

the voltage supply line coupled to the first power supply voltage selection circuit and the second power supply voltage selection circuit;

a first power supply voltage selection circuit selecting, as a drive voltage of the first word line driver, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line based on test data being written into or reading from the first memory cell;

a second power supply voltage selection circuit selecting, as the operating voltage supplied from the first power supply line to the first memory cell, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line based on test data being written into or reading from the first memory cell; and

an internal controller switching a mode of the SRAM circuit between a normal mode and a test mode by controlling the power supply voltage reduction circuit and the first and second power supply voltage selection circuits,

wherein, in the normal mode, the internal controller causes the first power supply voltage selection circuit and the second power supply voltage selection circuit to select the external power supply voltage,

wherein, in the test mode, the internal controller causes the first power supply voltage selection circuit to select the reduction voltage as the drive voltage of the first word line driver when writing test data into the first memory cell and to select the external power supply voltage as the drive voltage of the first word line driver when reading test data from the first memory cell, and causes the second power supply voltage selection circuit to select the external power supply voltage as the voltage supplied to the first power supply line when writing the test data and to select the reduction voltage as the voltage supplied to the first power supply line when reading the test data,

wherein the voltage supply line is arranged between the memory cell array and the column decoder in the second direction,

wherein the second power supply voltage selection circuit is individually arranged for each column of the memory cell array between the memory cell array and the column decoder, and

wherein the first power supply voltage selection circuit is arranged between the memory cell array and the row decoder, and is arranged in the second direction with respect to and adjacent to the second power supply voltage selection circuit.

2 . The semiconductor device according to claim 1 ,

wherein the SRAM circuit includes:

a second bit line pair extending in the first direction;

a second memory cell electrically connected to the second bit line pair and the first word line;

a second power supply line supplying an operating voltage to the second memory cell; and

a third power supply voltage selection circuit selecting one of the external power supply voltage or the reduction voltage as the operating voltage supplied to the second power supply line, and

wherein the internal controller causes the third power supply voltage selection circuit to select the reduction voltage as a voltage supplied to the second power supply line when reading the test data from the first memory cell in the test mode.

3 . The semiconductor device according to claim 1 ,

wherein the power supply power reduction voltage is capable of selecting, as the reduction voltage, a first reduction voltage and a second reduction voltage lower than the first reduction voltage.

4 . The semiconductor device according to claim 3 , further comprising a BIST (Built-in Self-Test) circuit,

wherein the BIST circuit determines whether test data written in the first memory cell in the test mode matches the test data read from the first memory cell after writing the test data in the test mode, and outputs a determination result.

5 . The semiconductor device according to claim 4 , further comprising a main controller receiving the determination result from the BIST circuit,

wherein the main controller records a lapsed time from beginning of use of the semiconductor device until an inconsistency between the written test data and the read test data occurs.

6 . The semiconductor device according to claim 5 ,

wherein the main controller predicts failure timing of the SRAM circuit in the semiconductor device based on the lapsed time when the first reduction voltage is selected as the reduction voltage and the lapsed time when the second reduction voltage is selected as the reduction voltage.

7 . The semiconductor device according to claim 6 ,

wherein the main controller outputs the predicted failure timing to an outside of the semiconductor device.

8 . The semiconductor device according to claim 3 ,

wherein the power supply voltage reduction circuit includes:

a first transistor connected between a power supply node receiving the external power supply voltage and an output node outputting the reduction voltage;

a second transistor connected between a ground node receiving a reference voltage and the output node; and

a third transistor connected to the second transistor in parallel,

wherein a current drive capability of the first transistor is larger than a current drive capability of the second transistor, and is larger than a current drive capability of the third transistor, and

wherein the current drive capability of the third transistor is larger than the current drive capability of the second transistor.

9 . The semiconductor device according to claim 1 ,

wherein the power supply voltage reduction circuit includes:

a first transistor connected between a power supply node receiving the external power supply voltage and an output node outputting the reduction voltage; and

a second transistor connected between a ground node receiving a reference voltage and the output node, and

wherein a current drive capability of the first transistor is larger than a current drive capability of the second transistor.

10 . A testing method for SRAM circuit,

the SRAM circuit comprising a power supply voltage reduction circuit generating a reduction voltage obtained by lowering an external power supply voltage and outputting the reduction voltage to a voltage supply line, a first power supply voltage selection circuit selecting, as a drive voltage of a first word line driver that drives a first word line connected to a first memory cell, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line, a second power supply voltage selection circuit selecting, as an operating voltage supplied from a first power supply line to the first memory cell, one of the external power supply voltage or the reduction voltage supplied from the voltage supply line, and an internal controller for setting the SRAM circuit to a test mode by controlling the power supply voltage reduction circuit and the first and second power supply voltage selection circuits,

the testing method being performed when the SRAM circuit is in the test mode,

the testing method comprising:

causing, by the internal controller, the first power supply voltage selection circuit to select the reduction voltage as the drive voltage of the first word line driver and causing, by the internal controller, the second power supply voltage selection circuit to select the external power supply voltage as the operating voltage supplied from the first power supply line to the first memory cell, and, in that state, writing first test data into the first memory cell;

causing, by the internal controller, the first power supply voltage selection circuit to select the external power supply voltage as the drive voltage of the first word line driver and causing, by the internal controller, the second power supply voltage selection circuit to select the reduction voltage as the operating voltage supplied from the first power supply line to the first memory cell, and, in that state, reading the first test data from the first memory cell; and

determining whether the written first test data matches the read first test data.

11 . The testing method according to claim 10 , further comprising:

in a state of supplying a second reduction voltage, which reduces the external power supply voltage as a drive voltage and is lower than the first reduction voltage, to the first word line driver and in a state of supplying the external power supply voltage to the first power supply line, writing second test data in the first memory cell;

in a state of supplying the external power supply voltage as a drive voltage to the first word line driver and in a state of supplying the second reduction voltage to the first power supply line, reading the written second test data from the first memory cell;

determining whether the written second test data matches the read second test data;

measuring a lapsed time from beginning of use of the SRAM circuit until an inconsistency between respective pieces of the first test data and the second test data occurs; and

predicting failure timing of the SRAM circuit based on the measured lapsed time.