Adaptive error avoidance in the memory devices
An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
1 . A method comprising:
receiving, by a processing device, a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device;
obtaining a plurality of default block family error avoidance (BFEA) threshold voltage offset values to be applied to a plurality of logical programming levels;
obtaining, based on a value of a data state metric associated with the set of memory cells, a plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels; and
for each logical programming level of the plurality of logical programming levels, applying, by the memory access operation, a combination of a default BFEA threshold voltage value associated with a respective logical programming level, a sub-BFEA threshold voltage value associated with the respective logical programming level, and a base voltage level associated with the respective logical programming level.
2 . The method of claim 1 , wherein obtaining, based on the value of the data state metric associated with the set of memory cells, the plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels comprises:
determining whether the value of the data state metric satisfies a threshold criterion; and
responsive to determining that the value of the data state metric satisfies the threshold criterion, determining, for each logical programming level of the plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value.
3 . The method of claim 2 , wherein the threshold criterion specifies a threshold ratio of the value of data state metric to an aggregate historic value of the data state metric.
4 . The method of claim 2 , wherein the threshold criterion specifies a threshold value of the data state metric.
5 . The method of claim 1 , wherein the data state metric is represented by a raw bit error rate (RBER).
6 . The method of claim 1 , wherein the sub-BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding sub-BFEA threshold voltage offset value to be applied at a predetermined logical programming level.
7 . The method of claim 1 , wherein the BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding BFEA threshold voltage offset value to be applied at a predetermined logical programming level.
8 . A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
receiving, by a processing device, a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device;
obtaining a plurality of default block family error avoidance (BFEA) threshold voltage offset values to be applied to a plurality of logical programming levels;
obtaining, based on a value of a data state metric associated with the set of memory cells, a plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels; and
for each logical programming level of the plurality of logical programming levels, applying, by the memory access operation, a combination of a default BFEA threshold voltage value associated with a respective logical programming level, a sub-BFEA threshold voltage value associated with the respective logical programming level, and a base voltage level associated with the respective logical programming level.
9 . The system of claim 8 , wherein obtaining, based on the value of the data state metric associated with the set of memory cells, the plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels comprises:
determining whether the value of the data state metric satisfies a threshold criterion; and
responsive to determining that the value of the data state metric satisfies the threshold criterion, determining, for each logical programming level of the plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value.
10 . The system of claim 9 , wherein the threshold criterion specifies a threshold ratio of the value of data state metric to an aggregate historic value of the data state metric.
11 . The system of claim 9 , wherein the threshold criterion specifies a threshold value of the data state metric.
12 . The system of claim 8 , wherein the data state metric is represented by a raw bit error rate (RBER).
13 . The system of claim 8 , wherein the sub-BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding sub-BFEA threshold voltage offset value to be applied at a predetermined logical programming level.
14 . The system of claim 8 , wherein the BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding BFEA threshold voltage offset value to be applied at a predetermined logical programming level.
15 . A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving, by a processing device, a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device;
obtaining a plurality of default block family error avoidance (BFEA) threshold voltage offset values to be applied to a plurality of logical programming levels;
obtaining, based on a value of a data state metric associated with the set of memory cells, a plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels; and
for each logical programming level of the plurality of logical programming levels, applying, by the memory access operation, a combination of a default BFEA threshold voltage value associated with a respective logical programming level, a sub-BFEA threshold voltage value associated with the respective logical programming level, and a base voltage level associated with the respective logical programming level.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein obtaining, based on the value of the data state metric associated with the set of memory cells, the plurality of sub-BFEA threshold voltage offset values to be applied to the plurality of logical programming levels comprises:
determining whether the value of the data state metric satisfies a threshold criterion; and
responsive to determining that the value of the data state metric satisfies the threshold criterion, determining, for each logical programming level of the plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value.
17 . The non-transitory computer-readable storage medium of claim 16 , wherein the threshold criterion specifies a threshold ratio of the value of data state metric to an aggregate historic value of the data state metric.
18 . The non-transitory computer-readable storage medium of claim 15 , wherein the data state metric is represented by a raw bit error rate (RBER).
19 . The non-transitory computer-readable storage medium of claim 15 , wherein the sub-BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding sub-BFEA threshold voltage offset value to be applied at a predetermined logical programming level.
20 . The non-transitory computer-readable storage medium of claim 15 , wherein the BFEA threshold voltage offset value is determined using a metadata structure comprising a plurality of records, each record of the plurality of records specifying, for each TAP bin of a plurality of TAP bins, a corresponding BFEA threshold voltage offset value to be applied at a predetermined logical programming level.