IP Library Granted Patent US 12688970
Granted Patent B2
US 12688970 · App. 18/093,832 · Granted Jul 21, 2026

Multilayer capacitor, multilayer capacitor group, and method for manufacturing multilayer capacitor

Inventor: Yukihiro Fujita (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/232H01G4/30
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Quick Facts
Patent No.
US 12688970
App. No.
18/093,832
Granted
Jul 21, 2026
Kind
B2
Abstract

A multilayer capacitor includes a capacitor body including dielectric layers, first and second internal electrodes, and first and second main surfaces, first and second external electrodes on at least one of the first and second main surfaces, first via conductors to electrically connect the first external electrode and the first internal electrodes, and second via conductors to electrically connect the second external electrode and the second internal electrodes, a direction in which the dielectric layer, the first internal electrode, and the second internal electrode are laminated is a height direction of the capacitor body, and a height of the capacitor body is about 100%, and a height of the first and second external electrodes is equal to or larger than about 50% with respect to the height of the capacitor body.

Claims (57)

1 . A multilayer capacitor comprising:

a capacitor body including a plurality of dielectric layers that are laminated, a plurality of first internal electrodes, and a plurality of second internal electrodes, the capacitor body including a first main surface and a second main surface opposed to each other;

a plurality of first external electrodes and a plurality of second external electrodes on at least one of the first main surface and the second main surface;

a plurality of first via conductors to electrically connect the first external electrode and the plurality of first internal electrodes; and

a plurality of second via conductors to electrically connect the second external electrode and the plurality of second internal electrodes; wherein

the second internal electrode includes a through hole, and the first via conductor is insulated from the second internal electrode, the first via conductor penetrates through the through hole;

the first internal electrode includes a through hole, and the second via conductor is insulated from the first internal electrode, the second via conductor penetrates through the through hole; and

a direction in which the dielectric layer, the first internal electrode, and the second internal electrode are laminated is defined as a height direction of the capacitor body, and the height of the capacitor body is set to 100%;

each of heights of the first external electrode and the second external electrode is equal to or larger than about 50% with respect to the height of the capacitor body;

each of the plurality of first external electrodes and the plurality of second external electrodes includes a plated electrode portion that is directly connected to a portion of the corresponding plurality of first via conductors or plurality of second via conductors;

the portion of the corresponding plurality of first via conductors or plurality of second via conductors is made of a conductive paste; and

when viewed at the direct connection of the plurality of first and second external electrodes and the plurality of first and second via conductors in the height direction, a surface area of at least one of the plurality of first external electrodes and the plurality of second external electrodes is equal or substantially equal to a surface area of the corresponding plurality of first via conductors or plurality of second via conductors.

2 . The multilayer capacitor according to claim 1 , wherein the height of the capacitor body is equal to or less than about 200 μm.

3 . The multilayer capacitor according to claim 1 , wherein each of the first external electrode and the second external electrode includes a plated-only electrode.

4 . The multilayer capacitor according to claim 1 , wherein

the plurality of dielectric layers include ceramic as a main component;

each of the first internal electrode, the second internal electrode, the first via conductor, and the second via conductor includes Ni as a main component; and

with respect to a total volume of the capacitor body, a volume of Ni included in the first internal electrode, the second internal electrode, the first via conductor, and the second via conductor is equal to or larger than about 25.0 vol %.

5 . The multilayer capacitor according to claim 1 , wherein a Sn film is on each of at least a portion of an outer surface of the first internal electrode and at least a portion of an outer surface of the second internal electrode.

6 . The multilayer capacitor according to claim 1 , wherein the first external electrode and the second external electrode are on both of the first main surface and the second main surface.

7 . The multilayer capacitor according to claim 1 , wherein the first external electrode and the second external electrode are on the second main surface, and are not on the first main surface.

8 . The multilayer capacitor according to claim 1 , wherein

the capacitor body includes:

a capacitance formation region in which the plurality of dielectric layers, the plurality of first internal electrodes, and the plurality of second internal electrodes are laminated;

a lower protection region including a dielectric layer of the plurality of dielectric layers at a side of the first main surface of the capacitor body; and

a dummy internal electrode is inside the lower protection region, the dummy internal electrode being electrically connected to neither the first via conductor nor the second via conductor.

9 . The multilayer capacitor according to claim 1 , wherein

the capacitor body includes:

a capacitance formation region in which the plurality of dielectric layers, the plurality of first internal electrodes, and the plurality of second internal electrodes are laminated;

an upper protection region including a dielectric layer of the plurality of dielectric layers at a side of the second main surface of the capacitor body; and

a dummy internal electrode inside the upper protection region, the dummy internal electrode being electrically connected to neither the first via conductor nor the second via conductor.

10 . The multilayer capacitor according to claim 1 , wherein

the capacitor body includes:

a capacitance formation region in which the plurality of dielectric layers, the plurality of first internal electrodes, and the plurality of second internal electrodes are laminated;

an upper protection region including a dielectric layer of the plurality of dielectric layers at a side of the second main surface of the capacitor body; and

both the first via conductor and the second via conductor penetrate through the upper protection region.

11 . The multilayer capacitor according to claim 8 , wherein a composition of the plurality of dielectric layers in the capacitance formation region is different from a composition of the dielectric layer in the lower protection region.

12 . The multilayer capacitor according to claim 1 , wherein

a surface roughness of the first main surface is larger than a surface roughness of the second main surface.

13 . The multilayer capacitor according to claim 1 , wherein a singulated adhesive sheet is attached to the first main surface.

14 . A multilayer capacitor group comprising:

a carrier sheet;

an adhesive layer on one main surface of the carrier sheet; and

a plurality of the multilayer capacitors according to claim 1 ; wherein

the plurality of multilayer capacitors are held by the carrier sheet with the first main surface being adhered to the adhesive layer.

15 . The multilayer capacitor group according to claim 14 , wherein the carrier sheet has stretchability in a surface direction.

16 . The multilayer capacitor group according to claim 14 , wherein the adhesive layer is an adhesive sheet having adhesiveness on both surfaces and having stretchability in a surface direction.

17 . The multilayer capacitor group according to claim 16 , wherein, after cutting the adhesive sheet for each of the plurality of multilayer capacitors, when each of the plurality of multilayer capacitors is to be peeled off from the carrier sheet, each of the plurality of multilayer capacitors is peeled off from the carrier sheet with the individually cut adhesive sheet adhering at a side of each of the plurality of multilayer capacitors.

18 . The multilayer capacitor group according to claim 14 , wherein the plurality of multilayer capacitors held by the carrier sheet with the first main surfaces bonded to the adhesive layer are held by the carrier sheet at intervals from each other.

19 . A method for manufacturing a multilayer capacitor, the method comprising:

preparing a base;

forming a conductive layer on an outer surface of the base;

preparing a plurality of unfired green sheet multilayer bodies in which a first main surface and a second main surface that are opposed to each other are provided, a conductive paste pattern that forms a first internal electrode and a conductive paste pattern that forms a second internal electrode are formed at an interlayer, a through hole penetrating through the first main surface and the second main surface is filled with a conductive paste that forms a first via conductor, and another through hole penetrating through between the first main surface and the second main surface is filled with a conductive paste that forms a second via conductor;

attaching the first main surface of the plurality of unfired green sheet multilayer bodies to the conductive layer of the base;

producing a plurality of capacitor bodies in which the plurality of unfired green sheet multilayer bodies are formed in a state where the plurality of unfired green sheet multilayer bodies are attached to the conductive layer of the base, and the first internal electrode and the second internal electrode are formed at the interlayer, and the first via conductor electrically connected to the first internal electrode, and the second via conductor electrically connected to the second internal electrode are formed to penetrate through the first main surface and the second main surface;

applying a current into the conductive layer and applying electrolytic plating to the first via conductor and the second via conductor that are exposed from the second main surface of the capacitor body; and

forming a first external electrode electrically connected to the first via conductor and a second external electrode electrically connected to the second via conductor, the first external electrode and the second external electrode having heights equal to or larger than about 50% with respect to a height of the capacitor body when the height of the capacitor is set to 100%.