Stripline wafer for wafer based connector system
A multilayer stripline wafer for use in an electrical connector. The multilayer stripline wafer includes multiple layers. Signal transmission pathways are positioned on at least one internal layer of the multiple layers. The signal transmission pathways may be uncoupled or loosely coupled singe ended single ended signal transmission pathways or differentially coupled signal transmission pathways. Conductive planar members are positioned in one or more layers of the multiple layers. The conductive planar members are spaced from the signal transmission pathways. One or more conductive planar members controls the impedance of the signal transmission pathways.
1 . A multilayer stripline wafer for use in an electrical connector, the multilayer stripline wafer comprising:
a mating interface and an mounting interface;
multiple layers;
signal transmission pathways positioned in at least one internal layer of the multiple layers, the signal transmission pathways having signal conductive pads positioned proximate but spaced from the mating interface;
conductive planar members positioned in one or more layers of the multiple layers;
floating pads extending between the mating interface and the signal conductive pads, the floating pads do not physically engaged the signal conductive pads, the floating pads being capacitively coupled to an internal ground layer of the multilayer stripline wafer and a beam area of a mating contact.
2 . The multilayer stripline wafer as recited in claim 1 , wherein the signal transmission pathways are single ended signal transmission pathways.
3 . The multilayer stripline wafer as recited in claim 1 , wherein the signal transmission pathways are coupled signal transmission pathways.
4 . The multilayer stripline wafer as recited in claim 1 , wherein the multilayer stripline wafer is a printed circuit board.
5 . The multilayer stripline wafer as recited in claim 1 , wherein a first ground plane member extends over a first surface of the wafer.
6 . The multilayer stripline wafer as recited in claim 5 , wherein openings are provided in the first ground plane member to expose the signal conductive pads.
7 . The multilayer stripline wafer as recited in claim 1 , wherein a second ground plane member is positioned in a layer of the one or more layers which is positioned proximate to the floating pads.
8 . The multilayer stripline wafer as recited in claim 1 , wherein lengths of the signal transmission pathways are matched for skew compensation.
9 . The multilayer stripline wafer as recited in claim 2 , wherein the transmission pathways are narrow to allow for increased routing density.
10 . The multilayer stripline wafer as recited in claim 1 , wherein the multilayer stripline wafer has at least one internal conductive planar member.
11 . The multilayer stripline wafer as recited in claim 10 , wherein at least one of the internal conductive planar members is positioned in a beam receiving area of the multilayer stripline wafer.
12 . The multilayer stripline wafer as recited in claim 10 , wherein at least one of the internal conductive planar members is a ground planar member.
13 . The multilayer stripline wafer as recited in claim 2 , wherein the single ended signal transmission pathways are routed between two layers of the conductive planar members.
14 . The multilayer stripline wafer as recited in claim 1 , wherein a slot extends from the mating interface, a mating interface of the multilayer stripline wafer, the slot configured to interact with a strengthening member of a mating connector to provide accurate alignment between the multilayer stripline wafer and the mating connector.
15 . The multilayer stripline wafer as recited in claim 1 , wherein stitched ground vias follow the routing of the signal transmission lines, traces or pathways.
16 . He multilayer stripline wafer as recited in claim 1 , wherein the conductive planar members are ground plane members which act as heatsinks.