Undervoltage-lockout circuit with low power consumption

1 . An undervoltage-lockout circuit, comprising:

a current mirror circuit, coupled to a system high voltage, and comprising a first connection terminal and a second connection terminal;

a current source, coupled to the first connection terminal;

a first reference transistor, wherein a first terminal of the first reference transistor is coupled to the second connection terminal, and a second terminal of the first reference transistor provides a reference voltage;

a second reference transistor, wherein a first terminal of the second reference transistor is coupled to the second terminal of the first reference transistor, and a second terminal of the second reference transistor is coupled to a system low voltage; and

a comparison circuit, coupled to the second terminal of the first reference transistor and the first connection terminal, configured to receive an input voltage at the first connection terminal and the reference voltage, and generating an undervoltage-lockout signal according to the input voltage and the reference voltage.

2 . The undervoltage-lockout circuit according to claim 1 , wherein:

each of the first reference transistor and the second reference transistor is implemented by N-type MOS FET,

the first reference transistor works in a weak inversion region, and

the second reference transistor works in a linear region.

3 . The undervoltage-lockout circuit according to claim 1 , wherein a voltage value of the reference voltage is determined based on a threshold voltage value of the first reference transistor and a threshold voltage value of the second reference transistor.

4 . The undervoltage-lockout circuit according to claim 1 , wherein the current mirror circuit further comprises:

a first current mirror transistor, wherein a first terminal of the first current mirror transistor is coupled to the system high voltage, and a second terminal of the first current mirror transistor is coupled to the first connection terminal and a control terminal of the first current mirror transistor; and

a second current mirror transistor, wherein a first terminal of the second current mirror transistor is coupled to the system high voltage, a second terminal of the second current mirror transistor is coupled to the second connection terminal, and a control terminal of the second current mirror transistor is coupled to the first connection terminal.

5 . The undervoltage-lockout circuit according to claim 4 , wherein a control terminal of the first reference transistor and a control terminal of the second reference transistor are coupled to the second connection terminal.

6 . The undervoltage-lockout circuit according to claim 1 , wherein the current mirror circuit further comprises:

a first current mirror transistor, wherein a first terminal of the first current mirror transistor is coupled to the system high voltage, and a second terminal of the first current mirror transistor is coupled to the first connection terminal and the first current mirror transistor;

a second current mirror transistor, wherein a first terminal of the second current mirror transistor is coupled to the system high voltage, a second terminal of the second current mirror transistor is coupled to the current source, and a control terminal of the second current mirror transistor is coupled to the first connection terminal; and

a third current mirror transistor, wherein a first terminal of the third current mirror transistor is coupled to the system high voltage, a second terminal of the third current mirror transistor is coupled to the second connection terminal, and a control terminal of the third current mirror transistor coupled to the first connection terminal.

7 . The undervoltage-lockout circuit according to claim 6 , wherein a control terminal of the first reference transistor and a control terminal of the second reference transistor are coupled to the second connection terminal.

8 . The undervoltage-lockout circuit according to claim 6 , wherein the current source comprises:

a first current source transistor, wherein a first terminal of the first current source transistor is coupled to the first connection terminal, and a control terminal of the first current source transistor is coupled to the second terminal of the second current mirror transistor;

a resistor, coupled between a second terminal of the first current source transistor and the system low voltage; and

a second current source transistor, wherein a first terminal of the second current source transistor is coupled to the second terminal of the second current mirror transistor, the control terminal of the first current source transistor, and the control terminal of the second current source transistor, and a second terminal of the second current source transistor is coupled to the system low voltage.

9 . The undervoltage-lockout circuit according to claim 8 , wherein a control terminal of the first reference transistor and a control terminal of the second reference transistor are coupled to the second terminal of the second current mirror transistor.

10 . The undervoltage-lockout circuit according to claim 1 , wherein the comparison circuit comprises:

a comparator, coupled to the second terminal of the first reference transistor and the first connection terminal, and configured to compare the input voltage with the reference voltage to generate a comparison signal; and

an inverting circuit, coupled to the comparator, and configured to generate the undervoltage-lockout signal according to the comparison signal.