IP Library › Granted Patent US 12689286

Granted Patent B2

US 12689286 · App. 18/981,159 · Granted Jul 21, 2026

Gate driver control for high frequency switching converter

Inventors: Wen-Jie Tsou (New Taipei City, TW); Bor-Tsang Hwang (New Taipei City, TW); Yu-Huei Lee (New Taipei City, TW); Haoyang You (San Jose, CA)

Assignee: Monolithic Power Systems, Inc.

H02M1/088 H02M3/157 H02M3/158 H03K17/6871 H03K4/06 H03K7/08

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Quick Facts

Patent No.: US 12689286
App. No.: 18/981,159
Granted: Jul 21, 2026
Kind: B2

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Abstract

A gate driver circuit includes a high side driver circuit, a low side driver circuit, and an on-time control circuit. The high side driver circuit provides a first gate driving signal to a high side power switch. The low side driver circuit provides a second gate driving signal to a low side power switch. The on-time control circuit is configured to provide the first on-time adjusting signal in response to the first on-time control signal and the second feedback signal. The on-time of the first on-time adjusting signal is greater than the on-time of the first on-time control signal. The on-time control circuit is further configured to provide the second on-time adjusting signal in response to the second on-time control signal and the second feedback signal. The on-time of the second on-time adjusting signal is greater than the on-time of the second on-time control signal.

Claims (60)

1 . A gate driver circuit for a switching converter, and the gate driver circuit comprises:

a high side driver circuit configured to provide a first gate driving signal to a high side power switch of the switching converter;

a low side driver circuit configured to provide a second gate driving signal to a low side power switch of the switching converter; and

an on-time control circuit configured to receive a first on-time control signal and a second feedback signal indicating a status of the second gate driving signal, and provide the first on-time adjusting signal in response to the first on-time control signal and the second feedback signal, wherein the first gate driving signal is generated in response to the first on-time adjusting signal, and an on-time of the first on-time adjusting signal is greater than the on-time of the first on-time control signal;

wherein the on-time control circuit is further configured to receive a second on-time control signal and a first feedback signal indicating a status of the first gate driving signal, and provide the second on-time adjusting signal in response to the second on-time control signal and the second feedback signal, wherein the second gate driving signal is generated in response to the second on-time adjusting signal, and an on-time of the second on-time adjusting signal is greater than the on-time of the second on-time control signal.

2 . The gate driver circuit of claim 1 , wherein the on-time control circuit is further configured to generate a first on-time in response to the first feedback signal and the first on-time control signal.

3 . The gate driver circuit of claim 2 , wherein the on-time control circuit is further configured to generate a first set signal, wherein the first set signal is at a high logic level when the first on-time control signal is at the high logic level, and the first set signal transitions to a low logic level when a high logic level of the first feedback signal is received, wherein the first on-time adjusting signal is at the high logic level when the first set signal is at the high logic level, and the first on-time adjusting signal transitions to the low logic level when the high logic level of the second feedback signal is received, wherein the high side power switch is turned on in response to the high logic level of the first on-time adjusting signal, and turned off in response to the low logic level of the first on-time adjusting signal.

4 . The gate driver circuit of claim 1 , wherein the on-time control circuit is further configured to generate a second on-time in response to the second feedback signal and the second on-time control signal.

5 . The gate driver circuit of claim 4 , wherein the on-time control circuit is further configured to generate a second set signal, where in the second set signal is at a high logic level when the second on-time control signal is at the high logic level, and the second set signal transitions to a low logic level when a high logic level of the second feedback signal is received, wherein the second on-time adjusting signal is at the high logic level when the second set signal is at the high logic level, and the second on-time adjusting signal transitions to the low logic level when the high logic level of the first feedback signal is received, wherein the low side power switch is turned on in response to the high logic level of the second on-time adjusting signal, and turned off in response to the low logic level of the second on-time adjusting signal.

6 . The gate driver circuit of claim 1 , wherein the on-time control circuit comprises:

a first delay circuit configured to receive the first on-time adjusting signal and provide the first feedback signal; and

a second delay circuit configured to receive the second on-time adjusting signal and provide the second feedback signal.

7 . The gate driver circuit of claim 1 , wherein the on-time control circuit comprises:

a first logic circuit having a first input terminal configured to receive the first on-time control signal, a second input terminal configured to receive the first feedback signal, and an output terminal configured to provide a first set signal;

a second logic circuit having a first input terminal configured to receive the first set signal, a second input terminal configured to receive the second feedback signal, and an output terminal configured to provide the first on-time adjusting signal;

a third logic circuit having a first input terminal configured to receive the second on-time control signal, a second input terminal configured to receive the second feedback signal, and an output terminal configured to provide a second set signal; and

a fourth logic circuit having a first input terminal configured to receive the second set signal, a second input terminal configured to receive the first feedback signal, and an output terminal configured to provide the second on-time adjusting signal.

8 . The gate driver circuit of claim 1 , wherein the first on-time adjusting signal is at a high logic level when the first on-time control signal is at the high logic level, and the first on-time adjusting signal transitions to a low logic level when a high logic level of the second feedback signal is received, wherein the second feedback signal is generated in response to the second on-time adjusting signal and a second delay, wherein the high side power switch is turned on in response to the high logic level of the first on-time adjusting signal, and turned off in response to the low logic level of the first on-time adjusting signal.

9 . The gate driver circuit of claim 1 , wherein the second on-time adjusting signal is at a high logic level when the second on-time control signal is at the high logic level, and the second on-time adjusting signal transitions to a low logic level when the high logic level of the first feedback signal is received, wherein the first feedback signal is generated in response to the first on-time adjusting signal and a first delay, wherein the low side power switch is turned on in response to the high logic level of the second on-time adjusting signal, and turned off in response to the low logic level of the second on-time adjusting signal.

10 . The gate driver circuit of claim 1 , wherein the on-time control circuit comprises:

a first logic circuit having a first input terminal configured to receive the first on-time control signal, a second input terminal configured to receive the second feedback signal, and an output terminal configured to provide the first on-time adjusting signal;

a second logic circuit having a first input terminal configured to receive the first on-time adjusting signal, a second input terminal configured to receive a first delay, and an output terminal configured to provide the first feedback signal;

a third logic circuit having a first input terminal configured to receive the second on-time control signal, a second input terminal configured to receive the first feedback signal, and an output terminal configured to provide the second on-time adjusting signal; and

a fourth logic circuit having a first input terminal configured to receive the second on-time adjusting signal, a second input terminal configured to receive a second delay, and an output terminal configured to provide the second feedback signal.

11 . A gate driver circuit for a switching converter, and the gate driver circuit comprises:

a high side driver circuit configured to provide a first gate driving signal to a high side power switch of the switching converter;

a low side driver circuit configured to provide a second gate driving signal to a low side power switch of the switching converter; and

an on-time control circuit configured to receive a first on-time control signal and a first feedback signal indicating a status of the first gate driving signal, and provide the first on-time adjusting signal in response to the first on-time control signal and the first feedback signal, wherein the first gate driving signal is generated in response to the first on-time adjusting signal;

wherein the on-time control circuit is further configured to receive a second on-time control signal and a second feedback signal indicating a status of the second gate driving signal, and provide the second on-time adjusting signal in response to the second on-time control signal and the second feedback signal, wherein the second gate driving signal is generated in response to the second on-time adjusting signal.

12 . The gate driver circuit of claim 11 , further comprising:

a first level shifter configured to receive the first gate driving signal and provide the first feedback signal; and

a second level shifter configured to receive the second gate driving signal and provide the second feedback signal.

13 . The gate driver circuit of claim 11 , wherein the first on-time adjusting signal is at a high logic level when the first on-time control signal is at the high logic level, and the first on-time adjusting signal transitions to a low logic level when a high logic level of the first feedback signal is received.

14 . The gate driver circuit of claim 13 , wherein the on-time control circuit is further configured to generate a first driver signal, the first driver signal is at the high logic level when the first on-time adjusting signal is at the high logic level, and the first driver signal transitions to the low logic level when the high logic level of the second feedback signal is received, wherein the high side power switch is turned on in response to the high logic level of the first driver signal, and turned off in response to the low logic level of the first driver signal.

15 . The gate driver circuit of claim 11 , wherein the on-time control circuit comprises:

a second logic circuit having a first input terminal configured to receive the first on-time adjusting signal, a second input terminal configured to receive the second feedback signal, and an output terminal configured to provide a first driver signal;

a fourth logic circuit having a first input terminal configured to receive the second on-time adjusting signal, a second input terminal configured to receive the first feedback signal, and an output terminal configured to provide a second driver signal.

16 . The gate driver circuit of claim 15 , wherein the on-time control circuit further comprises:

a first delay circuit configured to receive the first driver signal and provide the first feedback signal; and

a second delay circuit configured to receive the second driver signal and provide the second feedback signal.

17 . The gate driver circuit of claim 11 , wherein the second on-time adjusting signal is at a high logic level when the second on-time control signal is at the high logic level, and the second on-time adjusting signal transitions to a low logic level when a high logic level of the second feedback signal is received.

18 . The gate driver circuit of claim 17 , wherein the on-time control circuit is further configured to generate a second driver signal, the second driver signal is at the high logic level when the second on-time adjusting signal is at the high logic level, and the second driver signal transitions to a low logic level when the high logic level of the first feedback signal is received, wherein the low side power switch is turned on in response to the high logic level of the second driver signal, and turned off in response to the low logic level of the second driver signal.

19 . A gate driver circuit for a switching converter, and the gate driver circuit comprises:

a high side driver circuit configured to provide a first gate driving signal to a high side power switch of the switching converter;

a low side driver circuit configured to provide a second gate driving signal to a low side power switch of the switching converter; and

wherein the on-time control circuit is further configured to receive a second on-time control signal and a first feedback signal indicating a status of the first gate driving signal, and provide the second on-time adjusting signal in response to the second on-time control signal and the second on-time adjusting signal, wherein the second gate driving signal is generated in response to the second on-time adjusting signal;

wherein the first feedback signal is generated in response to the first on-time adjusting signal and a first delay; and

wherein the second feedback signal is generated in response to the second on-time adjusting signal and a second delay.

20 . The gate driver circuit of claim 19 , wherein the first on-time adjusting signal is at a high logic level when the first on-time control signal is at the high logic level, and the first on-time adjusting signal transitions to a low logic level when a high logic level of the second feedback signal is received, wherein the high side power switch is turned on in response to the high logic level of the first on-time adjusting signal, and turned off in response to the low logic level of the first on-time adjusting signal.

21 . The gate driver circuit of claim 20 , wherein the second feedback signal is at the high logic level when the second on-time adjusting signal is at the high logic level, and the second feedback signal transitions to the low logic level in response to the second delay.

22 . The gate driver circuit of claim 19 , wherein the second on-time adjusting signal is at a high logic level when the second on-time control signal is at the high logic level, and the second on-time adjusting signal transitions to a low logic level when the high logic level of the first feedback signal is received, wherein the low side power switch is turned on in response to the high logic level of the second on-time adjusting signal, and turned off in response to the low logic level of the second on-time adjusting signal.

23 . The gate driver circuit of claim 22 , wherein the first feedback signal is at the high logic level when the first on-time adjusting signal is at the high logic level, and the first feedback signal transitions to the low logic level in response to the first delay.

24 . The gate driver circuit of claim 19 , wherein the on-time control circuit comprises: