Low voltage floating inverter amplifier (LVFIA) and switched capacitor analog-to-digital converter (ADC)
Provided are a low voltage floating inverter amplifier (LVFIA) and a switched capacitor analog-to-digital converter (ADC). The LVFIA includes a first self-biased inverter, a second self-biased inverter, and an energy-storage capacitor that are connected in parallel. The first and second self-biased inverters are clock-controlled inverters that generate a bias voltage. The parallel connection has one end connected to a supply voltage through a reset switch and the other end connected to a grounding voltage through a reset switch. An input terminal and an input terminal of the second self-biased inverter are connected to an input signal and to the grounding voltage through a reset switch. An output terminal and an output terminal of the second self-biased inverter are equipped with an amplification switch. The reset switch and the amplification switch are alternately closed. The LVFIA achieves compatibility with sub-1V power supply, reducing a power consumption and improving energy efficiency.
1 . A low voltage floating inverter amplifier (LVFIA), comprising a first self-biased inverter, a second self-biased inverter, and an energy-storage capacitor C RES , wherein both the first self-biased inverter and the second self-biased inverter are clock-controlled inverters capable of generating a bias voltage; and the first self-biased inverter, the second self-biased inverter, and the energy-storage capacitor C RES are connected in parallel, one end of the parallel connection is connected to a supply voltage V DD through a reset switch, and the other end of the parallel connection is connected to a grounding voltage V SS through a reset switch;
both an input terminal of the first self-biased inverter and an input terminal of the second self-biased inverter are connected to an input signal and to the grounding voltage V SS through a reset switch; both an output terminal of the first self-biased inverter and an output terminal of the second self-biased inverter are equipped with an amplification switch to control output of an output signal; and the reset switch and the amplification switch are alternately closed through clock control;
the first self-biased inverter comprises a capacitively-biased P-channel metal oxide semiconductor (PMOS) circuit and a capacitively-biased N-channel metal oxide semiconductor (NMOS) circuit, wherein the capacitively-biased PMOS circuit is connected to the supply voltage V DD through the reset switch, and the capacitively-biased NMOS circuit is connected to the grounding voltage V SS through the reset switch; one end of the capacitively-biased PMOS circuit is connected to one end of the capacitively-biased NMOS circuit, wherein a connection point is connected to an input voltage and to the grounding voltage V SS through the reset switch, and the other end of the capacitively-biased PMOS circuit is connected to the other end of the capacitively-biased NMOS circuit through the amplification switch; and the second self-biased inverter and the first self-biased inverter are mirrored;
the capacitively-biased PMOS circuit comprises a first auto-zeroing capacitor C C1 and a PMOS transistor, wherein the first auto-zeroing capacitor C C1 is connected to a gate of the PMOS transistor, with a connection point provided with a first charging switch and a first bias switch, the first charging switch is connected to the grounding voltage V SS , and the first bias switch is connected to a drain of the PMOS transistor; a source of the PMOS transistor is connected to a source of a PMOS transistor of the second self-biased inverter, with a connection point separately connected to the energy-storage capacitor C RES and the reset switch; and the first charging switch and the first bias switch are alternately closed through the clock control;
the capacitively-biased NMOS circuit comprises a second auto-zeroing capacitor C C2 and an NMOS transistor, wherein the second auto-zeroing capacitor C C2 is connected to a gate of the NMOS transistor, with a connection point provided with a second charging switch and a second bias switch, the second charging switch is connected to the supply voltage V DD , and the second bias switch is connected to a drain of the NMOS transistor; a source of the NMOS transistor is connected to a source of an NMOS transistor of the second self-biased inverter, with a connection point separately connected to the energy-storage capacitor C RES and the reset switch; and the second charging switch and the second bias switch are alternately closed through the clock control; and
the first auto-zeroing capacitor C C1 is connected to the second auto-zeroing capacitor C C2 , with a connection point connected to the input voltage and to the grounding voltage V SS through the reset switch; and the drain of the PMOS transistor and the drain of the NMOS transistor are connected through the amplification switch.
2 . The LVFIA according to claim 1 , wherein a clock control timing sequence comprises a reset phase Φ RST and an amplification phase Φ EN , and the reset phase Φ RST comprises a capacitor charging phase Φ 1 and a bias voltage generation phase Φ 2 , wherein all reset switches are closed in the reset phase Φ RST to form a path, and are opened in the amplification phase Φ EN ; all charging switches are closed in the capacitor charging phase Φ 1 to form a path, and are opened in other phases; all bias switches are closed in the bias voltage generation phase Φ 2 to form a path, and opened in other phases; and all amplification switches are closed in the amplification phase Φ EN to form a path, and opened in the reset phase Φ RST .
3 . The LVFIA according to claim 2 , wherein in the bias voltage generation phase Φ 2 , all auto-zeroing capacitors are discharged, and a target bias voltage is obtained by controlling high-level time in the bias voltage generation phase Φ 2 ; and all PMOS transistors and NMOS transistors each achieve auto-zeroing to eliminate an offset voltage and 1/f noise.
4 . The LVFIA according to claim 3 , wherein in the bias voltage generation phase Φ 2 , a magnitude of a bias voltage generated by the discharging of all the auto-zeroing capacitors is related to the high-level time in the Φ 2 and a capacitance value of the auto-zeroing capacitor, specifically, longer high-level time in the Φ 2 leads to more electricity discharged by the auto-zeroing capacitor and a greater change of the generated bias voltage; and a larger capacitance value of the auto-zeroing capacitor leads to a slower change of the generated bias voltage.
5 . A switched capacitor analog-to-digital converter (ADC), comprising the LVFIA according to claim 4 .
6 . The switched capacitor ADC according to claim 5 , wherein the switched capacitor ADC is a ΣΔ ADC, the ΣΔ ADC comprises a second-order one-bit ΣΔ modulator, the second-order one-bit ΣΔ modulator comprises a first-stage integrator, a second-stage integrator, and a comparator, and both the first-stage integrator and the second-stage integrator comprise the LVFIA.
7 . The switched capacitor ADC according to claim 6 , wherein the second-order one-bit ΣΔ modulator comprises a pair of non-overlapping clocks Φ A and Φ B , and the non-overlapping clocks Φ A and Φ B are configured to control sampling and integration of the first-stage integrator and the second-stage integrator, and are also input to the LVFIA as reset and amplification clocks in the LVFIA; the reset clock of the LVFIA in the first-stage integrator comprises sub-clocks Φ 1 and Φ 2 that are respectively a capacitor charging phase and a bias voltage generation phase; and the reset clock of the LVFIA in the second-stage integrator comprises sub-clock Φ′ 1 and Φ′ 2 that are respectively a capacitor charging phase and a bias voltage generation phase.
8 . A switched capacitor analog-to-digital converter (ADC), comprising the LVFIA according to claim 3 .
9 . The switched capacitor ADC according to claim 8 , wherein the switched capacitor ADC is a ΣΔ ADC, the ΣΔ ADC comprises a second-order one-bit ΣΔ modulator, the second-order one-bit ΣΔ modulator comprises a first-stage integrator, a second-stage integrator, and a comparator, and both the first-stage integrator and the second-stage integrator comprise the LVFIA.
10 . The switched capacitor ADC according to claim 9 , wherein the second-order one-bit ΣΔ modulator comprises a pair of non-overlapping clocks Φ A and Φ B , and the non-overlapping clocks Φ A and Φ B are configured to control sampling and integration of the first-stage integrator and the second-stage integrator, and are also input to the LVFIA as reset and amplification clocks in the LVFIA; the reset clock of the LVFIA in the first-stage integrator comprises sub-clocks Φ 1 and Φ 2 that are respectively a capacitor charging phase and a bias voltage generation phase; and the reset clock of the LVFIA in the second-stage integrator comprises sub-clock Φ′ 1 and Φ′ 2 that are respectively a capacitor charging phase and a bias voltage generation phase.
11 . A switched capacitor analog-to-digital converter (ADC), comprising the LVFIA according to claim 2 .
12 . The switched capacitor ADC according to claim 11 , wherein the switched capacitor ADC is a ΣΔ ADC, the ΣΔ ADC comprises a second-order one-bit ΣΔ modulator, the second-order one-bit ΣΔ modulator comprises a first-stage integrator, a second-stage integrator, and a comparator, and both the first-stage integrator and the second-stage integrator comprise the LVFIA.
13 . The switched capacitor ADC according to claim 12 , wherein the second-order one-bit ΣΔ modulator comprises a pair of non-overlapping clocks PA and PB, and the non-overlapping clocks Φ A and Φ B are configured to control sampling and integration of the first-stage integrator and the second-stage integrator, and are also input to the LVFIA as reset and amplification clocks in the LVFIA; the reset clock of the LVFIA in the first-stage integrator comprises sub-clocks Φ 1 and Φ 2 that are respectively a capacitor charging phase and a bias voltage generation phase; and the reset clock of the LVFIA in the second-stage integrator comprises sub-clock Φ′ 1 and Φ′ 2 that are respectively a capacitor charging phase and a bias voltage generation phase.
14 . A switched capacitor analog-to-digital converter (ADC), comprising the LVFIA according to claim 1 .
15 . The switched capacitor ADC according to claim 14 , wherein the switched capacitor ADC is a ΣΔ ADC, the ΣΔ ADC comprises a second-order one-bit ΣΔ modulator, the second-order one-bit ΣΔ modulator comprises a first-stage integrator, a second-stage integrator, and a comparator, and both the first-stage integrator and the second-stage integrator comprise the LVFIA.
16 . The switched capacitor ADC according to claim 15 , wherein the second-order one-bit ΣΔ modulator comprises a pair of non-overlapping clocks Φ A and Φ B , and the non-overlapping clocks Φ A and Φ B are configured to control sampling and integration of the first-stage integrator and the second-stage integrator, and are also input to the LVFIA as reset and amplification clocks in the LVFIA; the reset clock of the LVFIA in the first-stage integrator comprises sub-clocks Φ 1 and Φ 2 that are respectively a capacitor charging phase and a bias voltage generation phase; and the reset clock of the LVFIA in the second-stage integrator comprises sub-clock Φ′ 1 and Φ′ 2 that are respectively a capacitor charging phase and a bias voltage generation phase.