Temperature-compensated envelope detector circuit

1 . An envelope detector circuit comprising:

an envelope extracting portion comprising a first connection node, a second connection node, a signal input node configured to receive an input voltage, a biasing node, and an extraction branch comprising an extraction module having a first extraction transistor and a second extraction transistor, wherein:

the first extraction transistor and the second extraction transistor are coupled to an intermediate node,

the first extraction transistor comprises a first current conduction terminal coupled to the first connection node, a second current conduction terminal coupled to the intermediate node, and a control terminal coupled to the signal input node and to the biasing node, and

the second extraction transistor comprises a first current conduction terminal coupled to the intermediate node, a second current conduction terminal coupled to the second connection node; and a control terminal coupled to the biasing node; and

a temperature compensating portion having a first compensation output node and a second compensation output node,

wherein the first compensation output node is directly connected to the second connection node,

wherein the second compensation output node is connected to the biasing node, and

wherein the temperature compensating portion includes a first temperature compensating transistor, the first temperature compensating transistor being diode-connected, coupled between the first and second compensation output nodes and configured to operate in a subthreshold condition.

2 . The envelope detector circuit according to claim 1 , wherein the temperature compensating portion further comprises:

a second temperature compensating transistor, the second temperature compensating transistor being diode-connected and coupled between a supply line and the second compensation output node,

a third temperature compensating transistor, the third temperature compensating transistor being mirror-like coupled to the second temperature compensating transistor and coupled between the supply line and the second compensation output node;

a fourth temperature compensating transistor, the fourth temperature compensating transistor being mirror-like coupled to the first temperature compensating transistor and coupled between the first and second compensation output nodes;

a fifth temperature compensating transistor, the fifth temperature compensating transistor being diode-connected and coupled between the first compensation output node and a reference potential line; and

a resistor element coupled between the fourth temperature compensating transistor and the first compensation output node.

3 . The envelope detector circuit according to claim 2 , wherein the first, the fourth and the fifth temperature compensating transistors are NMOS type transistors, and the second and the third temperature compensating transistors are PMOS type transistors.

4 . The envelope detector circuit of claim 2 , wherein the first and fourth temperature compensating transistors comprise a respective gate region each characterized by respective widths and lengths, wherein a ratio between the width and length of the gate region of the fourth temperature compensating transistor is N times a ratio between the width and length of the gate region of the first temperature compensating transistor, with N greater than 1.

5 . The envelope detector circuit according to claim 1 , wherein the extraction module is a first extraction module and the extraction branch comprises a plurality of further extraction modules, the first extraction module and the plurality of further extraction modules being cascade-coupled.

6 . The envelope detector circuit according to claim 1 , wherein the first current conduction terminal of the first extraction transistor is coupled to a detector output of the envelope detector circuit, and the second current conduction terminal of the second extraction transistor is coupled to the second connection node.

7 . The envelope detector circuit according to claim 6 , wherein:

the extraction branch is a first extraction branch;

the extraction module is a first extraction module;

the envelope extracting portion comprises a second extraction branch; and

the second extraction branch includes a second extraction module comprising:

a third extraction transistor having a first current conduction terminal coupled to the first connection node, a second current conduction terminal coupled to the intermediate node, and a control terminal coupled to the signal input node and to the biasing node, and

a fourth extraction transistor having a first current conduction terminal coupled to the intermediate node, a second current conduction terminal coupled to the second connection node, and a control terminal coupled to the biasing node.

8 . The envelope detector circuit according to claim 7 , wherein the first current conduction terminal of the third extraction transistor is coupled to the second connection node and the second current conduction terminal of the fourth extraction transistor is coupled to the detector output.

9 . An envelope detector comprising:

a proportional to absolute temperature (PTAT) bias circuit comprising a diode-connected transistor configured to conduct a PTAT current, and a first bias transistor having a conduction terminal coupled to a gate of the diode-connected transistor, wherein the gate of the diode-connected transistor is coupled to a conduction terminal bias node and a gate of the first bias transistor is coupled to a gate bias node;

a first detection branch comprising:

a first transistor having a conduction path coupled between the conduction terminal bias node and a first intermediate node, and a gate resistively coupled to the gate bias node and capacitively coupled to an RF input node, and

a second transistor having a conduction path coupled between the first intermediate node and a first detector output node, and a gate coupled to the gate bias node, wherein the first intermediate node is capacitively coupled to the RF input node; and

a second detection branch comprising:

a third transistor having a conduction path coupled between the conduction terminal bias node and a second intermediate node, and a gate coupled to the gate bias node, and

a fourth transistor having a conduction path coupled between the second intermediate node and a second detector output node, and a gate resistively coupled to the gate bias node and capacitively coupled to the RF input node, wherein the second intermediate node is capacitively coupled to the RF input node,

wherein the first detector output node and the second detector output node are configured to provide a differential signal representative of an envelope of a signal at the RF input node.

10 . The envelope detector of claim 9 , wherein the conduction terminal bias node and the gate bias node are configured to bias the first transistor, the second transistor, the third transistor, and the fourth transistor to have a temperature compensated channel resistance.

11 . The envelope detector of claim 9 , wherein noise generated by the PTAT bias circuit is configured to have a higher power in a common mode portion of a signal generated by the first detector output node and the second detector output node than in the differential signal representative of the envelope of the signal at the RF input node.

12 . The envelope detector of claim 9 , wherein the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors.

13 . The envelope detector of claim 9 , wherein the PTAT bias circuit further comprises:

a second bias transistor having a conduction path coupled between a power supply node and a third intermediate node, the second bias transistor being diode-connected;

a bias resistor having a first terminal coupled to a gate of the diode-connected transistor;

a third bias transistor having a conduction path coupled between the third intermediate node and a second terminal of the bias resistor; and

a fourth bias transistor having a conduction path coupled between the power supply node and a conduction path of the first bias transistor, wherein the first bias transistor is diode-connected.

14 . The envelope detector of claim 9 , further comprising:

a first capacitor coupled between the first detector output node and a reference node; and

a second capacitor coupled between the second detector output node and the reference node.

15 . An envelope detector circuit comprising:

an envelope extracting portion comprising a first connection node, a second connection node, a signal input node configured to receive an input voltage, a biasing node, and an extraction branch comprising an extraction module having a first extraction transistor and a second extraction transistor, wherein:

the first extraction transistor and the second extraction transistor are coupled to an intermediate node,

the first extraction transistor comprises a first current conduction terminal coupled to the first connection node, a second current conduction terminal coupled to the intermediate node, and a control terminal coupled to the signal input node and to the biasing node, and

the second extraction transistor comprises a first current conduction terminal coupled to the intermediate node, a second current conduction terminal coupled to the second connection node; and a control terminal coupled to the biasing node; and

a temperature compensating portion having a first compensation output node and a second compensation output node,

wherein the first compensation output node is directly connected to the second connection node,

wherein the second compensation output node is connected to the biasing node,

wherein the temperature compensating portion includes a first temperature compensating transistor; the first temperature compensating transistor being diode-connected, coupled between the first and second compensation output nodes and configured to operate in a subthreshold condition, and

wherein the temperature compensating portion includes a first filtering capacitor coupled between the second compensation output node and a reference potential line and a second filtering capacitor coupled between the first compensation output node and the reference potential line.

16 . The envelope detector circuit of claim 15 , wherein the temperature compensating portion further comprises:

a second temperature compensating transistor, the second temperature compensating transistor being diode-connected and coupled between a supply line and the second compensation output node;

a third temperature compensating transistor, the third temperature compensating transistor being mirror-like coupled to the second temperature compensating transistor and coupled between the supply line and the second compensation output node;

a fourth temperature compensating transistor, the fourth temperature compensating transistor being mirror-like coupled to the first temperature compensating transistor and coupled between the first and second compensation output nodes;

a fifth temperature compensating transistor, the fifth temperature compensating transistor being diode-connected and coupled between the first compensation output node and the reference potential line; and

a resistor element coupled between the fourth temperature compensating transistor and the first compensation output node.

17 . The envelope detector circuit of claim 16 , wherein the first, the fourth and the fifth temperature compensating transistors are NMOS type transistors, and the second and the third temperature compensating transistors are PMOS type transistors.

18 . The envelope detector circuit of claim 16 , further comprising a third filtering capacitor coupled between a respective gate terminal of the second and third temperature compensating transistors and the reference potential line.

19 . The envelope detector circuit of claim 16 , wherein the first and fourth temperature compensating transistors comprise a respective gate region each characterized by respective widths and lengths, wherein a ratio between the width and length of the gate region of the fourth temperature compensating transistor is N times a ratio between the width and length of the gate region of the first temperature compensating transistor, with N greater than 1.