IP Library › Granted Patent US 12,689,357
Granted Patent B2
US 12,689,357 · App. 18/458,703 · Granted Jul 21, 2026

Synchronizer flip-flop circuit

Inventors: Arnab Khawas (Bangalore, IN); Gokul Sabada (Bangalore, IN); Badarish Subbannavar (Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03K3/35625H03K3/012H03K3/0372
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Quick Facts
Patent No.
US 12,689,357
App. No.
18/458,703
Granted
Jul 21, 2026
Kind
B2
Abstract

Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

Claims (47)

1 . A device, comprising:

a first latch sub-circuit including a first inverter that includes a first transistor of a first type and a second transistor of a second type, wherein the first transistor and the second transistor each includes a control terminal, and wherein the control terminals of the first and second transistors are coupled to each other and configured to receive an input signal;

a first diode-connected transistor including a current path terminal and a control terminal, wherein the control terminal is coupled to the current path terminal, both of which are coupled to a body of the first transistor to decrease a voltage of the body of the first transistor during a transition of the input signal; and

a second diode-connected transistor including a current path terminal and a control terminal, wherein the control terminal is coupled to the current path terminal, both of which are coupled to a body of the second transistor.

2 . The device of claim 1 , comprising:

a second latch sub-circuit including a second inverter that includes a third transistor of the first type and a fourth transistor of the second type, wherein the third transistor and the fourth transistor each includes a control terminal, and wherein the control terminals of the third and fourth transistors are coupled to each other;

a third diode-connected transistor including a current path terminal and a control terminal, wherein the control terminal is coupled to the current path terminal, both of which are coupled to a body of the third transistor; and

a fourth diode-connected transistor including a current path terminal and a control terminal, wherein the control terminal is coupled to the current path terminal, both of which are coupled to a body of the fourth transistor.

3 . The device of claim 1 , wherein the first type is an N-type MOSFET, and wherein the second type is a P-type MOSFET.

4 . The device of claim 2 , comprising:

a transmission gate configured to:

receive an output signal from the first latch sub-circuit; and

transmit, or block transmission of, the output signal to the second latch sub-circuit.

5 . The device of claim 4 , wherein:

the control terminals of the third and fourth transistors are configured to receive the output signal transmitted by the transmission gate; and

the third diode-connected transistor is configured to decrease a voltage of the body of the third transistor during a transition of the output signal.

6 . The device of claim 5 , wherein:

the first latch sub-circuit includes a third inverter that includes a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor each includes a control terminal, and wherein the control terminals of the fifth and sixth transistors are coupled to each other and configured to receive an output signal from the first inverter;

the control terminal and the current path terminal of the first diode-connected transistor are coupled to a body of the fifth transistor; and

the control terminal and the current path terminal of the second diode-connected transistor are coupled to a body of the sixth transistor.

7 . The device of claim 6 , wherein:

the second latch sub-circuit includes a fourth inverter that includes a seventh transistor and an eighth transistor, wherein the seventh transistor and the eighth transistor each includes a control terminal, and wherein the control terminals of the seventh and eighth transistors are coupled to each other and configured to receive an output signal from the second inverter;

the control terminal and the current path terminal of the third diode-connected transistor are coupled to a body of the seventh transistor; and

the control terminal and the current path terminal of the fourth diode-connected transistor are coupled to a body of the eighth transistor.

8 . The device of claim 6 , wherein the fifth transistor and the sixth transistor of the third inverter each includes a current path terminal, and wherein the current path terminals of the fifth and sixth transistors are coupled to the transmission gate.

9 . The device of claim 5 , wherein:

the first latch sub-circuit includes a third inverter that includes a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor each includes a control terminal, and wherein the control terminals of the fifth and sixth transistors are coupled to each other and configured to receive the input signal;

the control terminal and the current path terminal of the first diode-connected transistor are coupled to a body of the fifth transistor; and

the control terminal and the current path terminal of the second diode-connected transistor are coupled to a body of the sixth transistor.

10 . The device of claim 9 , wherein:

the second latch sub-circuit includes a fourth inverter that includes a seventh transistor and an eighth transistor, wherein the seventh transistor and the eighth transistor each includes a control terminal, and wherein the control terminals of the seventh and eighth transistors are coupled to each other and configured to receive an output signal transmitted by the transmission gate;

the control terminal and the current path terminal of the third diode-connected transistor are coupled to a body of the seventh transistor; and

the control terminal and the current path terminal of the fourth diode-connected transistor are coupled to a body of the eighth transistor.

11 . The device of claim 9 , wherein the second transistor of the first inverter and the fifth transistor of the third inverter each includes a current path terminal, and wherein the current path terminals of the second and fifth transistors are coupled to the transmission gate.

12 . The device of claim 2 , comprising:

a transmission gate coupled in parallel with the first latch sub-circuit.

13 . The device of claim 2 , comprising:

a transmission gate coupled in parallel with the second latch sub-circuit.

14 . The device of claim 1 , comprising:

a transmission gate configured to:

receive the input signal; and

transmit, or block transmission of, the input signal to the first latch sub-circuit.

15 . The device of claim 14 , comprising:

a multiplexer configured to:

receive the input signal; and

transmit the input signal to the transmission gate.

16 . The device of claim 1 , wherein the first diode-connected transistor further includes a second current path terminal coupled to a supply voltage, and wherein the second diode-connected transistor further includes a second current path terminal coupled to ground.