Pulse width modulation decoder circuit, corresponding device and methods of operation
A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
1 . A method, comprising:
receiving a control signal having a first control value indicative of a reset phase and a second control value indicative of a duty cycle evaluation phase;
coupling an intermediate node to a data demodulation output node in response to the first control value of the control signal;
decoupling the intermediate node from the data demodulation output node in response to the second control value of the control signal; and
while the control signal has the second control value:
injecting a current into the intermediate node as a function of a first value of an input pulse width modulated (PWM) signal in a PWM period and sinking a current from the intermediate node as a function of a second value of that input PWM signal in the same PWM period, thereby changing the voltage across the capacitor;
comparing the changing voltage to a reference voltage; and
driving the data demodulation output node to generate a data demodulation output signal having a first output value or to a second output value in response to a result of said comparing.
2 . The method of claim 1 , further comprising alternating between the first and second control values for the control signal.
3 . The method of claim 1 , wherein comparing comprises applying the changing voltage to an input of an inverter circuit.
4 . The method of claim 3 , wherein the reference voltage is approximately one-half a supply voltage of the inverter circuit.
5 . The method of claim 1 , wherein comparing comprises applying the changing voltage to a first input of a differential comparison circuit and applying the reference voltage to a second input of the differential comparison circuit.
6 . The method of claim 1 , wherein said capacitor is coupled between the intermediate node and the output node.
7 . The method of claim 6 , wherein coupling the intermediate node to the data demodulation output node comprising connecting the intermediate node to the data demodulation output node by way of a transistor switch that is actuated in response to the first control value of the control signal.
8 . The method of claim 1 , wherein said capacitor is coupled between the intermediate node and a ground node.
9 . The method of claim 8 , wherein coupling the intermediate node to the data demodulation output node comprising connecting the intermediate node to the data demodulation output node by way of a transistor switch that is actuated in response to the first control value of the control signal.
10 . The method of claim 1 :
wherein injecting the current into the intermediate node comprises actuating a current source to source said current to the intermediate node in response to the first value of the input PWM signal; and
wherein sinking the current from the intermediate node comprises actuating a current source to sink said current from the intermediate node in response to the second value of the input PWM signal.
11 . The method of claim 1 , further comprising latching the first or second output value at an end of the duty cycle evaluation phase.
12 . The method of claim 1 , further comprising:
inverting the input PWM signal; and
inverting the data demodulation output signal.
13 . A method, comprising:
receiving an input pulse width modulated (PWM) signal at an input node;
generating a control signal having an alternating first control value and second control value;
operating a first decoder circuit that receives the input PWM signal in a reset phase when the control signal has the first control value and in a duty-cycle evaluation phase when the control signal has the second control value;
operating a second decoder circuit that receives the input PWM signal in the reset phase when the control signal has the second control value and in the duty-cycle evaluation phase when the control signal has the first control value; and
propagating to an output node an output signal of the first decoder circuit when the control signal has the second control value and propagating to the output node an output signal of the second decoder circuit when the control signal has the first control value.
14 . The method of claim 13 , further comprising latching a signal at the output node in response to an edge of the input PWM signal.
15 . The method of claim 13 , wherein said reset phase for each of the first and second decoder circuits comprises resetting a voltage across a capacitor to a reset voltage level.
16 . The method of claim 15 , wherein said duty-cycle evaluation phase for each of the first and second decoder circuits comprises:
injecting a current into the capacitor as a function of a first value of the input PWM signal in a PWM period and sinking a current from the capacitor as a function of a second value of that input PWM signal in the same PWM period;
comparing the voltage across the capacitor to a reference voltage; and
generating the output signal having a first output value or a second output value as a function of a result of said comparing.