Switching control
This application relates to methods and apparatus for switching control of semiconductor switches. In a switching circuit, a semiconductor switch is implemented as a composite switch having a plurality of switch elements, each having a respective gate electrode. A switch driver is configured to drive the gate electrodes of the switch elements to a first gate voltage over a duration of a first switch transition and is configured to enable drive of at least some of the gate electrodes of the plurality of semiconductor switch elements at different times in a temporal sequence during the first switch transition. The temporal sequence is configured to provide an average resistance of the composite switch over the duration of the first switch transition which is closer to a final composite switch resistance, compared to driving the gate electrodes of the switch elements at the same time as one another.
1 . A switching circuit comprising:
a first semiconductor switch, wherein the first semiconductor switch comprises a composite semiconductor switch having a plurality of semiconductor switch elements, each semiconductor switch element having a respective gate electrode; and
a switch driver configured to drive the gate electrodes of the plurality of semiconductor switch elements to a first gate voltage over a duration of a first switch transition of the first semiconductor switch;
wherein the switch driver is configured to enable drive of at least some of the gate electrodes of the plurality of semiconductor switch elements at different times in a temporal sequence during the first switch transition, said temporal sequence being configured to provide an average switch resistance for the first semiconductor switch over the duration of the first switch transition which is closer to a final switch resistance of the first semiconductor switch at the end of the first switch transition compared to driving the gate electrodes of the plurality of semiconductor switch elements at the same time as one another.
2 . The switching circuit of claim 1 wherein the first switch transition is a turn on transition of the first semiconductor switch and said temporal sequence is configured to provide a reduced average switch resistance for the first semiconductor switch over the duration of the first switch transition compared to driving the gate electrodes of the plurality of semiconductor switch elements at the same time as one another.
3 . The switching circuit of claim 2 wherein the first semiconductor switch is a composite NMOS switch and the plurality of semiconductor switch elements comprise NMOS switch elements.
4 . The switching circuit of claim 1 wherein the switch driver comprises a voltage generator for generating the first gate voltage.
5 . The switching circuit of claim 4 wherein said temporal sequence is based on a charge transfer capability of the voltage generator.
6 . The switching circuit of claim 5 further comprising a controller for controlling said temporal sequence, wherein said controller is configured to dynamically vary the temporal sequence in response to variation in the charge transfer capability of the voltage generator.
7 . The switching circuit of claim 4 wherein the voltage generator comprises a switching voltage generator configured to repeatedly operable in cycles of switching phases.
8 . The switching circuit of claim 7 wherein said temporal sequence is based on the cycles of switching phases of the voltage generator.
9 . The switching circuit of claim 4 wherein the voltage generator comprises a charge-pump.
10 . The switching circuit of claim 1 wherein the switch driver comprises a switch network for connecting the gate electrodes of the plurality of semiconductor switch elements to a gate drive signal and a controller configured to control said switch network during the first switch transition to implement said temporal sequence.
11 . The switching circuit of claim 10 wherein the controller is configured to dynamically control the temporal sequence based on one or more operating parameters.
12 . The switching circuit of claim 11 wherein said one or more operating parameters comprises a feedback signal indicative of a gate voltage of one of the plurality of semiconductor switch elements during the first switch transition.
13 . The switching circuit of claim 10 wherein the controller is configured to enable drive of a first one of the plurality of semiconductor switch elements and to determine when to subsequently enable drive of a second one of the plurality of semiconductor switch elements based on an indication of a gate voltage of the first one of the plurality of semiconductor switch elements.
14 . The switching circuit of claim 1 wherein the switch driver is further configured to drive the gate electrodes of the plurality of semiconductor switch elements to a second gate voltage during a second switch transition of the first semiconductor switch, wherein the second switch transition is an opposite transition to the first switch transition.
15 . The switching circuit of claim 14 wherein the switch driver is configured to enable drive of all of the gate electrodes of the plurality of semiconductor switch elements at the same time during the second switch transition.
16 . The switching circuit of claim 14 wherein the second switch transition is a turn off transition of the first semiconductor switch.
17 . The switching circuit of claim 1 wherein the first semiconductor switch is a high-side switch connected between a high-side voltage node and an output node and the switching circuit also comprises a second semiconductor switch which is a low-side switch connected between the output node and a low-side voltage node.
18 . The switching circuit of claim 1 implemented as part of a power regulator or switching driver.
19 . A switching circuit comprising:
a composite semiconductor switch having a plurality of semiconductor switch elements, each semiconductor switch element having a respective gate electrode; and
a switch driver configured to connect the gate electrodes of the plurality of semiconductor switch elements to a gate drive signal during a first switch transition of a first semiconductor switch, wherein the switch driver is configured to connect at least some of the gate electrodes of the plurality of semiconductor switch elements to the gate drive signal at different times in a temporal sequence to provide an accelerated change in switch resistance compared to connecting the gate electrodes of the plurality of semiconductor switch elements to the gate drive signal at the same time as one another.
20 . A switching circuit comprising:
a composite semiconductor switch having a plurality of semiconductor switch elements, each semiconductor switch element having a respective gate electrode; and
a switch driver configured to receive a gate drive signal from a gate drive supply,
wherein the switch driver is configured to connect the gate electrodes of the plurality of semiconductor switch elements to the gate drive signal during a first switch transition of a first semiconductor switch, and
wherein the switch driver is configured to control connection of the gate drive signal to the gate electrodes during said first switch transition in a temporal sequence based on a characteristic of the gate drive supply.
21 . A switching circuit as claimed in claim 20 wherein the connection of the gate drive signal to the gate electrodes in said temporal sequence is controlled to accelerate a change in resistance of the composite MOS switch based on the characteristic of the gate drive supply compared to connecting the gate drive signal to the gate electrodes of the plurality of semiconductor switch elements at the same time as one another.
22 . A switching circuit as claimed in claim 20 wherein the characteristic of the gate drive supply comprises one or more of: an instantaneous charge available from the gate drive supply, a current limit of the gate drive supply, a state of health or a state of charge of a battery of the gate drive supply.