Multi-slope switching circuit for switched-capacitor signal integrator

1 . An apparatus, comprising:

an integrator including a first input and a second input; and

a switched-capacitor, comprising:

a first capacitor;

a first multi-slope switching circuit coupled to a first plate of the first capacitor;

a first switching device coupled between a second plate of the first capacitor and a common mode node;

a second switching device coupled between the second plate of the first capacitor and the first input of the integrator;

a second capacitor;

a second multi-slope switching circuit coupled to a first plate of the second capacitor;

a third switching device coupled between a second plate of the second capacitor and the common mode node; and

a fourth switching device coupled between the second plate of the second capacitor and the second input of the integrator.

2 . The apparatus of claim 1 , wherein:

the first multi-slope switching circuit comprises fifth, sixth, and seventh switching devices, wherein the fifth switching device is coupled between a first reference voltage input and the first plate of the first capacitor, wherein the sixth and seventh switching devices are coupled in parallel between the first plate of the first capacitor and a second reference voltage input; and

the second multi-slope switching circuit comprises eighth, ninth, and tenth switching devices, wherein the eighth switching device is coupled between the first reference voltage input and the first plate of the second capacitor, wherein the ninth and tenth switching devices are coupled in parallel between the first plate of the second capacitor and the second reference voltage input.

3 . The apparatus of claim 2 , wherein:

the fifth switching device comprises a first p-channel field effect transistor (PFET) including a gate configured to receive a first clock signal; and

the eighth switching device comprises a second PFET including a gate configured to receive a second clock signal.

4 . The apparatus of claim 3 , wherein:

the first multi-slope switching circuit further comprises a first n-channel field effect transistor (NFET) coupled between the first reference voltage input and the first plate of the first capacitor, wherein the first NFET is configured to receive a third clock signal; and

the second multi-slope switching circuit further comprises a second NFET coupled between the first reference voltage input and the first plate of the second capacitor, wherein the first NFET is configured to receive a fourth clock signal.

5 . The apparatus of claim 4 , wherein:

the first clock signal is substantially complementary of the third clock signal; and

the second clock signal is substantially complementary of the fourth clock signal.

6 . The apparatus of claim 2 , wherein:

the fifth switching device comprises a first n-channel field effect transistor (NFET) including a gate configured to receive a first clock signal; and

the eighth switching device comprises a second NFET including a gate configured to receive a second clock signal.

7 . The apparatus of claim 2 , wherein:

the sixth switching device comprises a first n-channel field effect transistor (NFET);

the seventh switching device comprises a second NFET;

the ninth switching device comprises a third NFET; and

the tenth switching device comprises a fourth NFET.

8 . The apparatus of claim 7 , wherein:

the first NFET has a channel width to length ratio (W/L) less than a W/L of the second NFET; and

the third NFET has a W/L less than a W/L of the fourth NFET.

9 . The apparatus of claim 7 , wherein:

the first NFET includes a gate configured to receive a first clock signal;

the first multi-slope switching circuit comprises a first inverter coupled between the first plate of the second capacitor and the second reference voltage input, wherein the first inverter includes an input configured to receive a second clock signal, and an output coupled to a gate of the second NFET;

the third NFET includes a gate configured to receive a third clock signal; and

the second multi-slope switching circuit comprises a second inverter coupled between the first plate of the first capacitor and the second reference voltage input, wherein the second inverter is configured to receive a fourth clock signal, and wherein the second inverter includes an output coupled to a gate of the fourth NFET.

10 . The apparatus of claim 9 , wherein:

the first clock signal is substantially complementary of the second clock signal; and

the third clock signal is substantially complementary of the fourth clock signal.

11 . The apparatus of claim 1 , wherein:

the first switching device comprises a first n-channel field effect transistor (NFET) including a gate configured to receive a clock signal; and

the third switching device comprises a second NFET including a gate configured to receive the clock signal.

12 . The apparatus of claim 1 , wherein:

the second switching device comprises a first n-channel field effect transistor (NFET) including a gate configured to receive a clock signal; and

the fourth switching device comprises a second NFET including a gate configured to receive the clock signal.

13 . The apparatus of claim 1 , wherein the integrator comprises:

an operational amplifier including the first input and the second input;

a first feedback capacitor coupled between a first output and the first input of the operational amplifier; and

a second feedback capacitor coupled between a second output and the second input of the operational amplifier.

14 . The apparatus of claim 1 , wherein the switched-capacitor further comprises:

a third capacitor;

a fifth switching device coupled between a first signal input and a first plate of the third capacitor;

a sixth switching device coupled between the first plate of the third capacitor and the common mode node;

a seventh switching device coupled between the second plate of the third capacitor and the common mode node;

an eighth switching device coupled between the second plate of the third capacitor and the first input of the integrator;

a fourth capacitor;

a ninth switching device coupled between a second signal input and a first plate of the fourth capacitor;

a tenth switching device coupled between the first plate of the fourth capacitor and the common mode node;

an eleventh switching device coupled between the second plate of the fourth capacitor and the common mode node; and

a twelfth switching device coupled between the second plate of the fourth capacitor and the second input of the integrator.

15 . A method of processing first and second differential voltages, comprising:

in accordance with a first phase of operation:

performing a first voltage transition at a first plate of a first capacitor from the second differential voltage to the first differential voltage; and

performing a second voltage transition at a second plate of a second capacitor from the first differential voltage to the second differential voltage with a first slope for a first portion of the second voltage transition and with a second slope for a second portion of the second voltage transition, the first slope being different than the second slope.

16 . The method of claim 15 , wherein the first and second differential voltages comprise first and second reference voltages, respectively.

17 . The method of claim 15 , wherein the first differential voltage is higher than the second differential voltage.

18 . The method of claim 15 , wherein the first slope has a smaller negative slope than the second slope.

19 . The method of claim 15 , wherein performing the second voltage transition comprises:

turning on a first field effect transistor (FET) coupled between the first plate of the second capacitor and an input for the second differential voltage during the first portion of the second voltage transition; and

turning on a second FET coupled between the first plate of the second capacitor and the input for the second differential voltage during the second portion of the second voltage transition.

20 . The method of claim 15 , where in accordance with a second phase of operation:

performing a third voltage transition of the first plate of the first capacitor from the first differential voltage to the second differential voltage with a third slope for a first portion of the third voltage transition and with a fourth slope for a second portion of the third voltage transition, the third slope being different than the fourth slope; and

performing a fourth voltage transition at the second plate of the second capacitor from the second differential voltage to the first differential voltage.