Pipeline circuit and pipeline operating method

1 . A pipeline circuit, comprising:

a plurality of multiplier-accumulators, configured to receive a plurality of input signals, and perform summation of the plurality of input signals to generate a computation result;

a plurality of pre-stage gating circuits, wherein the computation results of the plurality of multiplier-accumulators is input to a corresponding pre-stage gating circuit;

a plurality of select circuits, each of the plurality of select circuits being coupled to a corresponding pre-stage gating circuit and the corresponding multiplier-accumulator,

wherein, an output end of the multiplier-accumulator is coupled to a first input end of the respective pre-stage gating circuit and a first input end of the respective select circuit, a second input end of the select circuit is coupled to an output end of the respective one of the plurality of pre-stage gating circuits;

an adder, in which an input of the adder is coupled to the outputs of the plurality of select circuits;

a gating circuit, coupled to an output of the adder, and output an output signal at an output end,

wherein in a first mode, the gating circuit receives a signal corresponding to the computation result that has been gated by the plurality of pre-stage gating circuits to output as the output signal; and

wherein in a second mode, the gating circuit receives a signal corresponding to the computation result that bypasses the plurality of pre-stage gating circuits to output as the output signal.

2 . The pipeline circuit according to claim 1 , wherein in the first mode, both the pre-stage gating circuit and the gating circuit receive a first clock signal at respective clock ends,

wherein in the second mode, the clock end of the pre-stage gating circuit is blocked, and the clock end of the gating circuit receives a second clock signal.

3 . The pipeline circuit according to claim 2 , wherein a frequency of the first clock signal is higher than a frequency of the second clock signal.

4 . A pipeline operating method, comprising:

perform summation of the plurality of input signals by a multiplier-accumulator to generate a computation result;

inputting the computation result of the multiplier-accumulator to a corresponding pre-stage gating circuit and a corresponding select circuit;

selectively providing a signal to an adder by the corresponding select circuit to perform computation;

receiving an input signal by a gating circuit coupled to an adder, and selectively outputting the input signal as an output signal,

wherein in a first mode, the input signal that has been gated by a plurality of pre-stage gating circuits respectively coupled to the plurality of multiplier-accumulators is received by the gating circuit to output as the output signal; and

wherein in a second mode, the input signal that bypasses the plurality of pre-stage gating circuits is received by the gating circuit to output as the output signal.

5 . The pipeline operating method according to claim 4 , comprising coupling an output end of the pre-stage gating circuit to an input end of the gating circuit in the first mode by a select circuit, and coupling an input end of the pre-stage gating circuit to the input end of the gating circuit in the second mode by the select circuit.

6 . The pipeline operating method according to claim 5 , comprising: in the first mode, providing a first clock signal to clock ends of the pre-stage gating circuit and the gating circuit, and

in the second mode, blocking the clock end provided to the pre-stage gating circuit, and providing a second clock signal to the clock end of the gating circuit.

7 . The pipeline operating method according to claim 6 , wherein a frequency of the first clock signal is higher than a frequency of the second clock signal.