IC with first and second functional circuits coupling only first circuits to output bond pads

Inventors: H. Pooya Forghani-zadeh (Dallas, TX); George Vincent Konnail (Addison, TX); Christopher Adam Opoczynski (Irving, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H03K19/1776 H03K19/017509 H03K19/1737

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Quick Facts

Patent No.: US 12689377
App. No.: 18/666,135
Granted: Jul 21, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Claims (27)

1 . An encapsulated integrated circuit comprising:

(a) a substrate of semiconductor material having a core area and a peripheral area;

(b) bond pads formed in the peripheral area, the bond pads including first and second input bond pads and an output bond pad;

(c) a first set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the first set having a first programmable function, each programmable digital logic transistor circuit of the first set having respective first and second inputs coupled to the first and second input bond pads respectively, and having a respective output coupled to the output bond pad;

(d) a second set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the second set having a second programmable function different than the first programmable function, each functional programmable digital logic transistor circuit of the second set having respective first and second inputs and having a respective output; and

(e) conductive material coupling the first and second input bond pads to the respective first and second inputs of the one or more programmable digital logic transistor circuits of the first set and coupling the output bond pad to the respective output of the one or more programmable digital logic transistor circuits of the first set.

2 . The encapsulated integrated circuit of claim 1 in which the conductive material includes a strap.

3 . The encapsulated integrated circuit of claim 1 in which the conductive material includes a fuse.

4 . The encapsulated integrated circuit of claim 1 in which the conductive material includes metal.

5 . The encapsulated integrated circuit of claim 1 in which the conductive material includes an upper level metal.

6 . The encapsulated integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more AND gates.

7 . The encapsulated integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more OR gates.

8 . The encapsulated integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more NAND gates.

9 . The encapsulated integrated circuit of claim 1 in which the first set of programmable digital logic transistor circuits includes one or more NOR gates.

10 . The encapsulated integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more AND gates.

11 . The encapsulated integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more OR gates.

12 . The encapsulated integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more NAND gates.

13 . The encapsulated integrated circuit of claim 1 in which the second set of programmable digital logic transistor circuits includes one or more NOR gates.

14 . The encapsulated integrated circuit of claim 1 in which the conductive material includes multiplexer circuits coupling the output bond pad to the respective output of the one or more programmable digital logic transistor circuits of the first set.

15 . The encapsulated integrated circuit of claim 1 in which the conductive material couples the first and second input bond pads to the respective first and second inputs of the one or more programmable digital logic transistor circuits of the second set.

16 . The encapsulated integrated circuit of claim 1 including a third set of one or more programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the third set having a third programmable function different from the first and second programmable functions, each programmable digital logic transistor circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output.

17 . The encapsulated integrated circuit of claim 1 including:

a third set of programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the third set having a programmable third function different from the first and second programmable functions, each programmable functional circuit of the third set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output; and

a fourth set of programmable digital logic transistor circuits formed in the core area, each programmable digital logic transistor circuit of the fourth set having a programmable fourth function different from the first, second, and third programmable functions, each programmable digital logic transistor circuit of the fourth set having respective first and second inputs coupled to the first and second input bond pads, and having a respective output.

18 . The encapsulated integrated circuit of claim 1 , further including a non-volatile memory for supplying control signals for programming the first and second sets of programmable digital logic transistor circuitry.

19 . The encapsulated integrated circuit of claim 18 , wherein the encapsulated integrated circuit is manufactured at a first time and in which the first and second sets of programmable digital logic transistor circuitry are programmed at a second time, the second time later than the first time.

20 . The encapsulated integrated circuit of claim 1 in which the output bond pad couples only to the respective output of the one or more programmable digital logic transistor circuits of the first set.