Method and system for buffering a reference voltage
In accordance with an embodiment, a circuit includes an amplifier comprising a first input coupled to a reference voltage node, a first buffer having an input coupled to an output of the amplifier, a second buffer having an input coupled to the output of the amplifier, and a capacitor. A method of operating the circuit includes during a first phase of operation: forming a first closed loop including the amplifier and the first buffer and excluding the capacitor and the second buffer, and sampling a voltage difference between an output of the second buffer and the reference voltage node across the capacitor; and during a second phase of operation, forming a second closed loop including the amplifier, the first buffer, and the capacitor with the sampled voltage difference stored thereon, and excluding the second buffer.
1 . A method of operating a circuit comprising an amplifier comprising a first input coupled to a reference voltage node, a first buffer having an input coupled to an output of the amplifier, a second buffer having an input coupled to the output of the amplifier, and a capacitor, the method comprising: during a first phase of operation: forming a first closed loop including the amplifier and the first buffer and excluding the capacitor and the second buffer, wherein the first buffer provides a first analog voltage to a second input of the amplifier, and sampling, by the capacitor, a voltage difference between an output of the second buffer and the reference voltage node, and during a second phase of operation, forming a second closed loop including the amplifier, the first buffer, and the capacitor with the sampled voltage difference stored thereon, and excluding the second buffer, wherein the first buffer provides a second analog voltage to the second input of the amplifier during the second phase of operation, wherein the second buffer operates in an open loop condition during the second phase of operation.
2 . The method of claim 1 , wherein the output of the second buffer is coupled to a capacitive load.
3 . The method of claim 1 , wherein:
forming the first closed loop comprises closing a first switch coupled between the output of the first buffer and the second input of the amplifier;
sampling the voltage difference comprises closing a second switch coupled between the reference voltage node and a first terminal of the capacitor, and closing a third switch coupled between the output of the second buffer and a second terminal of the capacitor; and
forming the second closed loop comprises closing a fourth switch coupled between the second input of the amplifier and the second terminal of the capacitor, and closing a fifth switch coupled between the output of the first buffer and the first terminal of the capacitor.
4 . The method of claim 3 , further comprising:
opening the fourth switch and the fifth switch during the first phase of operation; and
opening the first switch, the second switch and the third switch during the second phase of operation.
5 . The method of claim 1 , further comprising driving, by the output of the second buffer, a capacitive array of an analog-to-digital converter during the second phase of operation.
6 . The method of claim 1 , wherein, during the second phase of operation, the second closed loop has a lower bandwidth than the second buffer.
7 . A circuit, comprising: an amplifier comprising a first input coupled to a reference voltage node; a first buffer having an input coupled to an output of the amplifier; a second buffer having an input coupled to the output of the amplifier; a capacitor; and a controller configured to: during a first phase of operation: form a first closed loop including the amplifier and the first buffer and excluding the capacitor and the second buffer, wherein the first buffer is configured to provide a first analog voltage to a second input of the amplifier, cause the capacitor to sample a voltage difference between an output of the second buffer and the reference voltage node; and during a second phase of operation, form a second closed loop including the amplifier, the first buffer, and the capacitor with the sampled voltage difference stored thereon, and excluding the second buffer, wherein the first buffer is configured to provide a second analog voltage to the second input of the amplifier during the second phase of operation, wherein the second buffer operates in an open loop condition during the second phase of operation.
8 . The circuit of claim 7 , further comprising:
a first switch coupled between the output of the first buffer and the second input of the amplifier;
a second switch coupled between the reference voltage node and a first terminal of the capacitor;
a third switch coupled between the output of the second buffer and a second terminal of the capacitor;
a fourth switch coupled between the second input of the amplifier and the second terminal of the capacitor; and
a fifth switch coupled between the output of the first buffer and the first terminal of the capacitor.
9 . The circuit of claim 8 , wherein the controller is configured to:
during the first phase of operation:
close the first switch, the second switch and the third switch, and
open the fourth switch and the fifth switch; and
during the second phase of operation:
open the first switch, the second switch and the third switch, and
close the fourth switch and the fifth switch.
10 . The circuit of claim 8 , wherein the first input of the amplifier comprises a positive input, and the second input of the amplifier comprises a negative input.
11 . The circuit of claim 7 , wherein the first buffer is configured to be biased with a lower current than the second buffer.
12 . The circuit of claim 7 , wherein:
the first buffer comprises a first source follower amplifier; and
the second buffer comprises a second source follower amplifier.
13 . The circuit of claim 12 , wherein:
the first source follower amplifier comprises a first flipped voltage follower (FVF) circuit; and
the second source follower amplifier comprises a second FVF circuit.
14 . The circuit of claim 7 , wherein, during the second phase of operation, the second closed loop has a lower bandwidth than the second buffer.
15 . The circuit of claim 7 , wherein:
during the first phase of operation, an intrinsic offset voltage of the amplifier is stored on the capacitor; and
during the second phase of operation, the intrinsic offset voltage stored on the capacitor is subtracted from the second input of the amplifier.
16 . A circuit comprising:
an amplifier having a first input coupled to a reference voltage node and a second input;
a first buffer having an input coupled to an output of the amplifier;
a second buffer having an input coupled to the output of the amplifier;
a capacitor;
a first switch coupled between an output of the first buffer and the second input of the amplifier;
a second switch coupled between the first input of the amplifier and a first terminal of the capacitor;
a third switch coupled between an output of the second buffer and a second terminal of the capacitor;
a fourth switch coupled between the second input of the amplifier and the second terminal of the capacitor; and
a fifth switch coupled between the output of the first buffer and the first terminal of the capacitor.
17 . The circuit of claim 16 , further comprising a controller coupled to control nodes of the first switch, the second switch, the third switch, the fourth switch and the fifth switch, the controller configured to:
during a first phase of operation:
activate the first switch, the second switch and the third switch, and
deactivate the fourth switch and the fifth switch; and
during a second phase of operation:
deactivate the first switch, the second switch and the third switch, and
activate the fourth switch and the fifth switch.
18 . The circuit of claim 16 , wherein:
the amplifier comprises a folded cascode transconductance amplifier;
the first buffer comprises a first source follower amplifier; and
the second buffer comprises a second source follower amplifier.
19 . The circuit of claim 18 , wherein:
the first source follower amplifier comprises a first flipped voltage follower (FVF) circuit; and
the second source follower amplifier comprises a second FVF circuit.
20 . The circuit of claim 16 , wherein the second buffer is configured to have a higher bias current than the first buffer.