Comparator for analog to digital converter

1 . An analog to digital converter (ADC), comprising:

a first analog-to-digital convertor stage configured to:

convert a first analog signal to a first digital value;

output a residue signal based on the first digital value;

a second analog-to-digital convertor stage including a comparator connected to the first analog-to-digital stage and configured to:

receive the residue signal and output a second digital value;

shift the residue signal by an amount based on a delay between the output of the second digital value and a time of the first analog signal crossing an input reference signal; and

a combiner configured to:

receive the first digital value and the second digital value; and

combine the first digital value and the second digital value into an output representing a digital version of the first analog signal.

2 . The ADC of claim 1 , wherein the second analog-to-digital convertor stage includes a voltage level shifter circuit connected to the comparator.

3 . The ADC of claim 2 , wherein the voltage level shifter circuit includes:

a second comparator configured to output a third digital value based on the first digital value and the first analog signal;

an up/down counter configured to receive the third digital value and output a voltage offset based on the third digital value; and

a voltage level shifter configured to receive the voltage offset.

4 . The ADC of claim 3 , wherein the voltage level shifter circuit includes a one-shot circuit connected to the second comparator.

5 . The ADC of claim 2 , wherein the voltage level shifter circuit includes:

a second comparator configured to output a third digital value based on the first digital value and the first analog signal;

a signed accumulator configured to receive the third digital value and output a voltage offset based on the third digital value; and

an adder configured to receive the voltage offset.

6 . The ADC of claim 1 , wherein the comparator includes a mismatch circuit to shift the residue signal.

7 . The ADC of claim 6 , wherein the mismatch circuit includes:

a switched cap level shifter that receives the residue signal;

a first transistor connected to the switched cap level shifter; and

a second transistor that receives the input reference signal.

8 . A method for converting an analog signal to a digit value, comprising:

receiving, by a comparator, a first analog input signal and an input reference signal;

comparing, by the comparator, the first analog signal to the input reference signal;

outputting, by the comparator, a digital value based on the first analog signal crossing the input reference signal;

shifting the first analog signal by an amount based on a delay between the output of the digital value and a time of the first analog signal crossing the input reference signal; and

outputting the first digital value as a digital output signal representing at least a portion of the first analog input signal.

9 . The method of claim 8 , further comprising:

receiving the digital value by a second comparator;

outputting, by the comparator, a second digital value; and

determining a voltage offset based on the second digital value and the digital value, wherein the voltage offset indicates the amount to shift the first analog signal.

10 . The method of claim 9 , wherein an up/down counter determines the voltage offset.

11 . The method of claim 9 , wherein an accumulator determines the voltage offset.

12 . The method of claim 9 , wherein the voltage offset is configured to increase or decrease based on the digital value and the second digital value.

13 . The method of claim 12 , wherein the voltage offset increases based on the first analog signal being greater than the input reference signal and the digital value being high.

14 . The method of claim 8 , further comprising:

mismatching, within the comparator, the first analog signal.

15 . The method of claim 14 , wherein mismatching the first analog signal includes:

increasing or decreasing a number of active transistors, within the comparator, connected to the first analog signal.

16 . The method of claim 14 , wherein mismatching the first analog signal includes:

increasing or decreasing a number of active current sources, within the comparator, connected to the first analog signal.

17 . The method of claim 14 , wherein mismatching the first analog signal includes:

shifting a voltage level of the first analog signal using a switched cap level shifter.

18 . The method of claim 8 , further comprising:

converting an original analog signal to a first digital value through coarse conversion;

outputting the first analog signal as a residue signal to the comparator.

19 . An analog-to-digital convertor (ADC) comprising:

a cross detector configured to:

receive an input reference signal; and

output a first digital value;

a voltage shifter circuit including:

a comparator configured to:

receive an analog signal and the input reference signal; and

output a second digital value based on the first digital value and the analog signal;

an up/down counter configured to receive the second digital value and output a voltage offset based on the second digital value; and

a voltage level shifter configured to receive the voltage offset and output a shifted analog signal to the cross detector.

20 . The ADC of claim 19 , wherein the voltage level shifter shifts the analog signal by an amount based on a delay between the output of the first digital value and a time of the first analog signal crossing the input reference signal.