Switched capacitor slew boost technique
In described examples, a switched capacitor circuit includes an amplifier that generates a first output signal in response to a first sampled input signal. A second sampling circuit is coupled to the amplifier and generates an output signal in response to the first output signal. A first current boost circuit is coupled to the amplifier and the second sampling circuit and provides current to the second sampling circuit when the first output signal is below a first threshold. A second current boost circuit is coupled to the amplifier and the second sampling circuit and receives current from the second sampling circuit when the first output signal is above a second threshold.
1 . A switched capacitor circuit comprising:
an amplifier configured to generate a first output signal in response to a first sampled input signal;
a second sampling circuit coupled to the amplifier and configured to generate an output signal in response to the first output signal;
a first current boost circuit coupled to the amplifier and the second sampling circuit and configured to provide current to the second sampling circuit when the first output signal is below a first threshold, the first current boost circuit further including:
a PMOS transistor coupled to a first voltage source terminal;
a third switch coupled to a gate terminal of the PMOS transistor; and
a first capacitor coupled to the gate terminal of the PMOS transistor and the amplifier; and
a second current boost circuit coupled to the amplifier and the second sampling circuit configured to receive current from the second sampling circuit when the first output signal is above a second threshold, the second current boost circuit includes an NMOS transistor and the second threshold is greater than the first threshold, and a drain terminal of both the PMOS transistor and the NMOS transistor is coupled to the amplifier.
2 . The switched capacitor circuit of claim 1 further comprising a first sampling circuit coupled to the amplifier and configured to generate the first sampled input signal in response to an input signal.
3 . The switched capacitor circuit of claim 2 , wherein the first sampling circuit comprises:
a first switch configured to receive the input signal; and
a second capacitor having a top plate coupled to the first switch and the amplifier and having a bottom plate coupled to a ground terminal.
4 . The switched capacitor circuit of claim 3 , wherein the second sampling circuit comprises:
a second switch configured to receive the first output signal; and
a load capacitor having a top plate coupled to the second switch and having a bottom plate coupled to the ground terminal.
5 . The switched capacitor circuit of claim 4 , wherein the third switch is configured to receive a first bias voltage; and
a source terminal of the PMOS transistor is coupled to the first voltage source terminal, the first voltage source terminal configured to be coupled to a first voltage source.
6 . The switched capacitor circuit of claim 5 , wherein the second current boost circuit comprises:
a fourth switch coupled to a gate terminal of the NMOS transistor and configured to receive a second bias voltage; and
a second capacitor coupled to the gate terminal of the NMOS transistor and the amplifier, wherein a source terminal of the NMOS transistor is coupled to a second voltage source.
7 . The switched capacitor circuit of claim 6 is configured to operate in a first phase and a second phase, wherein in the first phase:
the first switch, the third switch and the fourth switch are closed and the second switch is opened;
the first sampling circuit generates the first sampled input signal in response to the input signal;
the amplifier generates the first output signal in response to the first sampled input signal;
the PMOS transistor and the NMOS transistor both operate in a cut-off region; and
the first output signal is sampled on the first capacitor and the second capacitor.
8 . The switched capacitor circuit of claim 7 , wherein in the second phase:
the second switch is closed and the first switch, the third switch and the fourth switch are opened;
the load capacitor receives current from the first voltage source through the PMOS transistor if the first output signal is below the first threshold; and
the load capacitor sinks current to the second voltage source through the NMOS transistor if the first output signal is above the second threshold.
9 . The switched capacitor circuit of claim 8 , wherein in the second phase when the first output signal is below the first threshold:
a voltage at each of the gate terminal of the PMOS transistor and the NMOS transistor is pulled below a first predefined value;
the NMOS transistor operates in the cut-off region; and
the PMOS transistor operates in one of a linear region and a saturation region.
10 . The switched capacitor circuit of claim 8 , wherein in the second phase when the first output signal is above the second threshold:
a voltage at each of the gate terminal of the PMOS transistor and the NMOS transistor is pulled above a second predefined value;
the PMOS transistor operates in the cut-off region; and
the NMOS transistor operates in one of a linear region and a saturation region.
11 . A method comprising:
generating a first output signal by an amplifier in response to a first sampled input signal;
generating an output signal by a second sampling circuit in response to the first output signal;
providing current to the second sampling circuit by a first current boost circuit when the first output signal is below a first threshold, the first current boost circuit includes a PMOS transistor and a first capacitor coupled to the PMOS transistor; and
receiving current from the second sampling circuit in a second current boost circuit when the first output signal is above a second threshold, the second current boost circuit includes an NMOS transistor and a second capacitor coupled to the NMOS transistor, and the second threshold is greater than the first threshold, and a drain terminal of both the PMOS transistor and the NMOS transistor is coupled to the amplifier.
12 . The method of claim 11 further comprising generating the first sampled input signal by a first sampling circuit in response to an input signal.
13 . The method of claim 12 , wherein generating the first sampled input signal further comprises:
closing a first switch; and
sampling the input signal on a second capacitor.
14 . The method of claim 11 , wherein the second sampling circuit includes a load capacitor.
15 . The method of claim 14 further comprising:
sampling the first output signal generated by the amplifier on the first capacitor and the second capacitor; and
operating the PMOS transistor and the NMOS transistor in a cut-off region.
16 . The method of claim 14 , wherein when the load capacitor is coupled to the amplifier:
providing current to the load capacitor through the PMOS transistor when the first output signal is below the first threshold; and
sinking current from the load capacitor through the NMOS transistor when the first output signal is above the second threshold.
17 . The method of claim 14 , wherein when the first output signal is below the first threshold:
pulling a voltage at each of a gate terminal of the PMOS transistor and the NMOS transistor below a first predefined value;
operating the NMOS transistor in a cut-off region; and
operating the PMOS transistor in one of a linear region and a saturation region.
18 . The method of claim 17 , wherein when the first output signal is above the second threshold:
pulling the voltage at each of the gate terminal of the PMOS transistor and the NMOS transistor above a second predefined value;
operating the PMOS transistor in the cut-off region; and
operating the NMOS transistor in one of a linear region and a saturation region.
19 . A computing device comprising:
a processing unit;
a memory module coupled to the processing unit; and
a transceiver coupled to the processing unit and the memory module, the transceiver having a switched capacitor circuit, the switched capacitor circuit comprising:
an amplifier configured to generate a first output signal in response to a first sampled input signal;
a second sampling circuit coupled to the amplifier and configured to generate an output signal in response to the first output signal;
a first current boost circuit coupled to the amplifier and the second sampling circuit and configured to provide current to the second sampling circuit when the first output signal is below a first threshold; and
a second current boost circuit coupled to the amplifier and the second sampling circuit and configured to receive current from the second sampling circuit when the first output signal is above a second threshold.
20 . The switched capacitor circuit of claim 10 , wherein the PMOS transistor and the NMOS transistor both configured to operate in the cut-off region responsive to the first output signal between the first threshold and the second threshold.
21 . The method of claim 17 further comprising operating the PMOS transistor and the NMOS transistor in the cut-off region when the first output signal is between the first threshold and the second threshold.