Hardware optimization device and method for low-density parity check decoder

1 . A hardware optimization device for optimizing a hardware of a low-density parity check (LDPC) decoder, comprising:

a variable node hardware block configured to operate in a multi-stage pipeline structure for updating a variable node message delivered to each variable node; and

a check node hardware block configured to operate in a multi-stage pipeline structure for updating a check node message delivered to each check node,

wherein the variable node hardware block and the check node hardware block divide a parity check matrix into N column blocks for the update (N is a natural number of 2 or more), repeatedly perform calculations for the variable node and the check node for each of the divided column blocks, and perform different calculations for variable nodes according to respective phases each corresponding to one of the divided column blocks, through a pipeline method,

wherein each of the respective phases comprise both the variable node calculations and the check node calculations for the corresponding column block, wherein each of the respective phases comprise a plurality of pipeline stages, wherein a first pipeline stage of an M th respective phase (M is a natural number of 2 or more) is calculated in parallel to a second pipeline stage of an M th −1 respective phase, and wherein the phase is divided to sequentially perform the variable node calculations and the check node calculations for the corresponding column block.

2 . The hardware optimization device of claim 1 , wherein the phase is an operation for each of the column blocks and is used as many times as the number of the column blocks for one iterative decoding.

3 . The hardware optimization device of claim 1 , wherein the variable node hardware block and the check node hardware block make the phase into a plurality of pipeline stages and consecutively perform two adjacent phase calculations with a timing offset as much as one clock cycle corresponding to one stage of the plurality of pipeline stages.

4 . The hardware optimization device of claim 1 , wherein the variable node hardware block and the check node hardware block increase the number of iterative decodings possible within a given time through parallelization of the parity check matrix based on grouping of the column blocks.

5 . The hardware optimization device of claim 4 , wherein the variable node hardware block and the check node hardware block group the N column blocks to constitute the M phases (M is a natural number of 2 or more).

6 . The hardware optimization device of claim 5 , wherein the variable node hardware block and the check node hardware block perform log-likelihood ratio (LLR) update of each bit of the variable node message and the check node message through iterative decoding using the M phases and perform error correction in a given clock cycle.

7 . The hardware optimization device of claim 4 , wherein each of the phases is provided such that the maximum number of each of check nodes and variable nodes is determined according to a grouping number of the column blocks.

8 . The hardware optimization device of claim 1 , wherein the variable node hardware block and the check node hardware block constitute iterative decoding by delivering the updated message to an adjacent node through an edge connecting the variable node and the check node.

9 . The hardware optimization device of claim 8 , wherein, when a value of the parity check matrix is 1, the edge is connected between the variable node and the check node.

10 . The hardware optimization device of claim 1 , wherein, in order to optimize hardware resources, the variable node hardware block and the check node hardware block define a bit width of each of a channel log-likelihood ratio (LLR), a soft LLR message (VCM) delivered from the variable node hardware block to the check node hardware block, and a soft LLR message (CVM) delivered from the check node hardware block to the variable node hardware block with 4 bits including a sign bit,

wherein, for an internal calculation, the variable node hardware block defines the bit width of each of the channel LLR, the VCM, and the CVM with 7 bits including the sign bit.

11 . A hardware optimization method for a low-density parity check (LDPC) decoder including a variable node hardware block configured to operate in a multi-stage pipeline structure for updating a variable node message delivered to each variable node, and a check node hardware block configured to operate in a multi-stage pipeline structure for updating a check node message delivered to each check node, the hardware optimization method comprising:

dividing a parity check matrix into N column blocks; and

repeatedly performing calculations for the variable node and the check node for each of the divided column blocks, wherein different calculations for variable nodes are performed according to respective phases each corresponding to one of the divided column blocks, through a pipeline method,

wherein each of the respective phases comprise both the variable node calculations and the check node calculations for the corresponding column block, wherein each of the respective phases comprise a plurality of pipeline stages, wherein a first pipeline stage of an M th respective phase (M is a natural number of 2 or more) is calculated in parallel to a second pipeline stage of an M th −1 respective phase, and wherein the phase is divided to sequentially perform the variable node calculations and the check node calculations for the corresponding column block.

12 . The hardware optimization method of claim 11 , wherein the phase is an operation for each of the column blocks and is used as many times as the number of the column blocks for one iterative decoding.

13 . The hardware optimization method of claim 11 , wherein the variable node hardware block and the check node hardware block make the phase into a plurality of pipeline stages and consecutively perform two adjacent phase calculations with a timing offset as much as one clock cycle corresponding to one stage of the plurality of pipeline stages.

14 . The hardware optimization method of claim 11 , wherein the variable node hardware block and the check node hardware block increase the number of possible iterative decodings within a given time through parallelization of the parity check matrix based on grouping of the column blocks.

15 . The hardware optimization method of claim 14 , wherein the variable node hardware block and the check node hardware block group the N column blocks to constitute the M phases.

16 . The hardware optimization method of claim 15 , wherein the variable node hardware block and the check node hardware block perform log-likelihood ratio (LLR) update of each bit of the variable node message and the check node message through iterative decoding using the M phases and perform error correction in a given clock cycle.

17 . The hardware optimization method of claim 14 , wherein each of the phases is provided such that the maximum number of each of check nodes and variable nodes is determined according to a grouping number of the column blocks.

18 . The hardware optimization method of claim 11 , wherein the variable node hardware block and the check node hardware block constitute iterative decoding by delivering the updated message to an adjacent node through an edge connecting the variable node and the check node.

19 . The hardware optimization method of claim 18 , wherein, when a value of the parity check matrix is 1, the edge is connected between the variable node and the check node.

20 . The hardware optimization method of claim 11 , wherein, in order to optimize hardware resources, the variable node hardware block and the check node hardware block define a bit width of each of a channel log-likelihood ratio (LLR), a soft LLR message (VCM) delivered from the variable node hardware block to the check node hardware block, and a soft LLR message (CVM) delivered from the check node hardware block to the variable node hardware block with 4 bits including a sign bit,

wherein, for an internal calculation, the variable node hardware block defines the bit width of each of the channel LLR, the VCM, and the CVM with 7 bits including the sign bit.