Wireless communication system and electronic device

1 . A system, comprising:

a first high-frequency integrated circuit;

an intermediate-frequency integrated circuit; and

an antenna array;

wherein the first high-frequency integrated circuit is coupled between the antenna array and the intermediate-frequency integrated circuit;

wherein the first high-frequency integrated circuit comprises:

a first high-frequency transceiver, a second high-frequency transceiver, a high-frequency phase-locked loop, a high-frequency controller, a first diplexer, and a second diplexer, wherein the first high-frequency transceiver is coupled to the first diplexer, the second high-frequency transceiver is coupled to the second diplexer, the high-frequency phase-locked loop is separately coupled to the first high-frequency transceiver and the second high-frequency transceiver, and the high-frequency controller is separately coupled to the first diplexer and the second diplexer;

wherein the intermediate-frequency integrated circuit comprises:

a first intermediate-frequency transceiver, a second intermediate-frequency transceiver, an intermediate-frequency phase-locked loop, an intermediate-frequency controller, a third diplexer, and a fourth diplexer, wherein the first intermediate-frequency transceiver is coupled to the third diplexer, the second intermediate-frequency transceiver is coupled to the fourth diplexer, the intermediate-frequency phase-locked loop is separately coupled to the first intermediate-frequency transceiver and the second intermediate-frequency transceiver, and the intermediate-frequency controller is separately coupled to the third diplexer and the fourth diplexer; and

wherein the first diplexer is coupled to the third diplexer, and the second diplexer is coupled to the fourth diplexer; and

wherein a control signal is transmitted between the high-frequency controller and the intermediate-frequency controller, wherein the control signal comprises an instruction data signal and an echo clock signal, a phase of the instruction data signal is synchronized with a phase of the echo clock signal, and a frequency of the instruction data signal and a frequency of the echo clock signal are in a co-frequency relationship or a frequency multiplication relationship; and

wherein the echo clock signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the first diplexer and the third diplexer, and the instruction data signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the second diplexer and the fourth diplexer.

2 . The system according to claim 1 , wherein the instruction data signal is sent out on a rising edge or a falling edge of the echo clock signal.

3 . The system according to claim 1 , wherein the intermediate-frequency controller transmits the echo clock signal to the high-frequency controller via the third diplexer and the first diplexer.

4 . The system according to claim 3 , wherein the first diplexer is further coupled to the high-frequency phase-locked loop; and

wherein the intermediate-frequency controller further transmits the echo clock signal to the high-frequency phase-locked loop via the third diplexer and the first diplexer, to provide a first reference clock signal for the high-frequency phase-locked loop.

5 . The system according to claim 1 , wherein the intermediate-frequency integrated circuit further comprises an intermediate-frequency pin, and the intermediate-frequency pin is configured to receive a second reference clock signal.

6 . The system according to claim 5 , wherein the intermediate-frequency pin is coupled to the intermediate-frequency phase-locked loop, and the second reference clock signal received by the intermediate-frequency pin provides the second reference clock signal for the intermediate-frequency phase-locked loop.

7 . The system according to claim 5 , wherein the echo clock signal transmitted by the intermediate-frequency controller is generated based on the second reference clock signal received by the intermediate-frequency pin.

8 . The system according to claim 1 , wherein the intermediate-frequency integrated circuit further comprises a synchronizer, configured to synchronize the instruction data signal and the echo clock signal;

wherein the synchronizer is coupled to the third diplexer, the fourth diplexer, and the intermediate-frequency controller, and the echo clock signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the first diplexer, the third diplexer, and the synchronizer; and

wherein the instruction data signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the second diplexer, the fourth diplexer, and the synchronizer.

9 . The system according to claim 1 , further comprising:

a second high-frequency integrated circuit, comprising: a third high-frequency transceiver, a fourth high-frequency transceiver, a second high-frequency phase-locked loop, a second high-frequency controller, a fifth diplexer, and a sixth diplexer; and

wherein the sixth diplexer is separately coupled to the first diplexer of the first high-frequency integrated circuit and the fifth diplexer of the second high-frequency integrated circuit, and the fourth diplexer is separately coupled to the second diplexer of the first high-frequency integrated circuit and the sixth diplexer of the second high-frequency integrated circuit.

10 . The system according to claim 9 , wherein both the first high-frequency integrated circuit and the second high-frequency integrated circuit comprise at least one addressing pin, and each addressing pin is configured to receive a high electrical level or a low electrical level, to distinguish between a chip code of the first high-frequency integrated circuit and a chip code of the second high-frequency integrated circuit.

11 . The system according to claim 1 , further comprising:

a second high-frequency integrated circuit, a first multi-way switch, and a second multi-way switch; and

wherein the second high-frequency integrated circuit comprises: a third high-frequency transceiver, a fourth high-frequency transceiver, a second high-frequency phase-locked loop, a second high-frequency controller, a fifth diplexer, and a sixth diplexer;

wherein the third diplexer is separately coupled to the first diplexer of the first high-frequency integrated circuit and the fifth diplexer of the second high-frequency integrated circuit via the first multi-way switch, and the first multi-way switch is configured to control the third diplexer to be conducted with the first diplexer of the first high-frequency integrated circuit or the fifth diplexer of the second high-frequency integrated circuit; and

wherein the fourth diplexer is separately coupled to the second diplexer of the first high-frequency integrated circuit and the sixth diplexer of the second high-frequency integrated circuit via the second multi-way switch, and the second multi-way switch is configured to control the fourth diplexer to be conducted with the second diplexer of the first high-frequency integrated circuit or the sixth diplexer of the second high-frequency integrated circuit.

12 . The system according to claim 1 , wherein the first diplexer comprises a high-pass filter and a low-pass filter, and both the high-pass filter and the low-pass filter comprise a respective first end and a respective second end;

wherein the first end of the high-pass filter is coupled to the first high-frequency transceiver, and the first end of the low-pass filter is coupled to the high-frequency controller;

wherein both the second end of the high-pass filter and the second end of the low-pass filter are coupled to a combination port of the third diplexer; and

wherein the high-pass filter allows a signal whose frequency is greater than a first frequency to pass, the low-pass filter allows a signal whose frequency is less than a second frequency to pass, and the first frequency is greater than the second frequency.

13 . The system according to claim 1 , wherein the first diplexer comprises a band-pass filter and a low-pass filter, and both the band-pass filter and the low-pass filter comprise a respective first end and a respective second end;

wherein the first end of the band-pass filter is coupled to the first high-frequency transceiver, and the first end of the low-pass filter is coupled to the high-frequency controller;

wherein both the second end of the band-pass filter and the second end of the low-pass filter are coupled to a combination port of the third diplexer; and

wherein the band-pass filter allows a signal whose frequency is greater than a third frequency and less than a fourth frequency to pass, the low-pass filter allows a signal whose frequency is less than a second frequency to pass, and the third frequency and the fourth frequency are greater than the second frequency.

14 . The system according to claim 13 , wherein the second frequency ranges from 100 MHz to 500 MHz.

15 . The system according to claim 1 , wherein the frequency of the instruction data signal or the frequency of the echo clock signal is one of 245.76 Mbps, 307.2 Mbps, or 491.52 Mbps.

16 . The system according to claim 1 , further comprising:

a first hardware line and a second hardware line; and

wherein the first diplexer and the third diplexer are coupled through the first hardware line, and the second diplexer and the fourth diplexer are coupled through the second hardware line; and

wherein the first hardware line or the second hardware line is a cable or a cable disposed in a circuit board.

17 . An electronic device, comprising:

a circuit board; and

a system, comprising:

a first high-frequency integrated circuit;

an intermediate-frequency integrated circuit; and

an antenna array;

wherein the first high-frequency integrated circuit is coupled between the antenna array and the intermediate-frequency integrated circuit;

wherein the first high-frequency integrated circuit comprises:

a first high-frequency transceiver, a second high-frequency transceiver, a high-frequency phase-locked loop, a high-frequency controller, a first diplexer, and a second diplexer, wherein the first high-frequency transceiver is coupled to the first diplexer, the second high-frequency transceiver is coupled to the second diplexer, the high-frequency phase-locked loop is separately coupled to the first high-frequency transceiver and the second high-frequency transceiver, and the high-frequency controller is separately coupled to the first diplexer and the second diplexer;

wherein the intermediate-frequency integrated circuit comprises:

a first intermediate-frequency transceiver, a second intermediate-frequency transceiver, an intermediate-frequency phase-locked loop, an intermediate-frequency controller, a third diplexer, and a fourth diplexer, wherein the first intermediate-frequency transceiver is coupled to the third diplexer, the second intermediate-frequency transceiver is coupled to the fourth diplexer, the intermediate-frequency phase-locked loop is separately coupled to the first intermediate-frequency transceiver and the second intermediate-frequency transceiver, and the intermediate-frequency controller is separately coupled to the third diplexer and the fourth diplexer; and

wherein the first diplexer is coupled to the third diplexer, and the second diplexer is coupled to the fourth diplexer; and

wherein a control signal is transmitted between the high-frequency controller and the intermediate-frequency controller, wherein the control signal comprises an instruction data signal and an echo clock signal, a phase of the instruction data signal is synchronized with a phase of the echo clock signal, and a frequency of the instruction data signal and a frequency of the echo clock signal are in a co-frequency relationship or a frequency multiplication relationship; and

wherein the echo clock signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the first diplexer and the third diplexer, and the instruction data signal is transmitted between the high-frequency controller and the intermediate-frequency controller via the second diplexer and the fourth diplexer.

18 . The electronic device according to claim 17 , wherein the instruction data signal is sent out on a rising edge or a falling edge of the echo clock signal.

19 . The electronic device according to claim 17 , wherein the intermediate-frequency controller transmits the echo clock signal to the high-frequency controller via the third diplexer and the first diplexer.

20 . The electronic device according to claim 19 , wherein the first diplexer is further coupled to the high-frequency phase-locked loop; and

wherein the intermediate-frequency controller further transmits the echo clock signal to the high-frequency phase-locked loop via the third diplexer and the first diplexer, to provide a first reference clock signal for the high-frequency phase-locked loop.