Opto-electronic assemblies

1 . An assembly of electronic components for reception of data using an optical fibre, wherein said assembly comprises:

a photodiode;

an amplifier coupled to said photodiode;

at least one feedback resistor coupled between an output and an input of said amplifier;

an arrangement of at least two MOS transistors, wherein said at least two MOS transistors are of the same channel polarity, and wherein said at least two MOS transistors are configured to be in parallel with said at least one feedback resistor;

a system for sensing a received input signal level, wherein said system is configured to apply a bias voltage to gates of said at least two MOS transistors, said bias voltage being varied by said system according to said received input signal level in a manner to control a resistance apparent through said arrangement of said at least two MOS transistors;

at least one capacitor configured to couple signals from an output of said amplifier to a gate of at least one of said at least two MOS transistors; and

at least one bias resistor configured to couple said bias voltage to a gate of at least one of said at least two MOS transistors.

2 . The assembly of electronic components as claimed in claim 1 , wherein said arrangement of said at least two MOS transistors comprises said at least two MOS transistors arranged so that their channel terminals are in parallel.

3 . The assembly of electronic components as claimed in claim 2 , wherein:

said at least one capacitor is coupled to said output of said amplifier via a first electronic switch; and

said at least one capacitor is coupled to a ground reference terminal via a second electronic switch, and

wherein a conducting condition of said first electronic switch is opposite to the conducting condition of said second electronic switch.

4 . The assembly of electronic components as claimed in claim 3 , wherein said system for sensing said received input signal level is further configured to provide control signals to set said conducting state of said first and second electronic switches.

5 . The assembly of electronic components as claimed in claim 1 , wherein said arrangement of said at least two MOS transistors comprises said at least two MOS transistors configured so that their channel terminals are in series.

6 . The assembly of electronic components as claimed in claim 5 , wherein:

a gate of a first of said at least two MOS transistors is coupled to receive said bias voltage from said sensing system;

a first channel terminal of said first of said at least two MOS transistors is coupled to an input of said amplifier;

a second channel terminal of said first of said at least two MOS transistors is coupled to a first channel terminal of a second of said at least two MOS transistors; and

a second channel terminal of said second of said at least two MOS transistors is coupled to said output of said amplifier.

7 . The assembly of electronic components as claimed in claim 6 , wherein:

said gate of said second of said at least two MOS transistors is coupled to said gate of the said first of said at least two MOS transistors via said at least one bias resistor; and

a gate of said second of said at least two MOS transistors is coupled to said output of said amplifier via said capacitor.

8 . The assembly of electronic components as claimed in claim 1 , wherein said same channel polarity comprises one of: n-channel and p-channel.

9 . A method for providing an assembly of electronic components for reception of data using an optical fibre, wherein said method comprises:

providing a photodiode;

providing an amplifier coupled to said photodiode;

providing at least one feedback resistor coupled between an output and an input of said amplifier;

providing an arrangement of at least two MOS transistors, wherein said at least two MOS transistors are of the same channel polarity, and wherein said at least two MOS transistors are configured to be in parallel with said resistor;

providing a system for sensing a received input signal level, wherein said system is configured to apply a bias voltage to gates of said at least two MOS transistors, said bias voltage being varied by said system according to said received input signal level in a manner to control a resistance apparent through an arrangement of said at least two MOS transistors;

providing at least one capacitor configured to couple signals from an output of said amplifier to a gate of at least one of said at least two MOS transistors; and

providing at least one bias resistor configured to couple said bias voltage to a gate of at least one of said at least two MOS transistors.

10 . The method as claimed in claim 9 , wherein providing said arrangement of said at least two MOS transistors comprises providing said at least two MOS transistors arranged so that their channel terminals are in parallel.

11 . The method as claimed in claim 10 , wherein providing said at least one capacitor comprises:

coupling said at least one capacitor to said output of said amplifier via a first electronic switch; and

coupling said at least one capacitor to a ground reference terminal via a second electronic switch, and

wherein a conducting condition of said first electronic switch is opposite to the conducting condition of said second electronic switch.

12 . The method as claimed in claim 11 , wherein providing said system for sensing said received input signal level further comprises providing control signals to set said conducting state of said first and second electronic switches.

13 . The method as claimed in claim 9 , wherein providing said arrangement of said at least two MOS transistors comprises providing said at least two MOS transistors arranged so that their channel terminals are in series.

14 . The method as claimed in claim 13 wherein providing said arrangement of said at least two MOS transistors comprises:

coupling a gate of a first of said at least two MOS transistors to receive said bias voltage from said sensing system;

coupling a first channel terminal of said first of said at least two MOS transistors to an input of said amplifier;

coupling a second channel terminal of said first of said at least two MOS transistors to a first channel terminal of a second of said at least two MOS transistors; and

coupling a second channel terminal of said second of said at least two MOS transistors to said output of said amplifier.

15 . The method as claimed in claim 14 , wherein providing said arrangement of said at least two MOS transistors comprises:

coupling said gate of said second of said at least two MOS transistors to said gate of the said first of said at least two MOS transistors via said at least one bias resistor; and

coupling a gate of said second of said at least two MOS transistors to said output of said amplifier via said capacitor.

16 . The method as claimed in claim 9 , wherein said same channel polarity is one of n-channel and p-channel.