LED display and pulse width modulation system therefor
A pulse width modulation system. Considering that a phase-locked loop can reduce a pulse width of a clock signal by increasing the frequency, in the present application, by means of a control voltage outputted by a filter in the phase-locked loop, an external second voltage-controlled retarder which has the same structure as a voltage-controlled retarder in the phase-locked loop can shift a phase of an original PWM signal backwards by a preset delay duration (less than one clock signal period) to obtain a signal to be superimposed. In this way, a target PWM signal of which the pulse width is the sum of the pulse width of the original PWM signal and the preset delay duration can be generated by superposing the signal to be superposed and the original PWM signal.
1 . A system for system for pulse width modulation, comprising:
clock-signal generating circuitry, configured to generate a clock signal;
pulse generating circuitry, configured to generate an original pulse width modulation (PWM) signal, of which a pulse width is a preset integer multiple of a period of the clock signal;
phase-locked circuitry, configured to generate a control voltage according to the clock signal;
a second voltage-controlled delayer, identical to a first voltage-controlled delayer in the phase-locked circuitry in structure, wherein the second voltage-controlled delayer is configured to delay, under excitation of the control voltage that is outputted by a filter in the phase-locked circuitry, the original PWM signal in phase by preset delay duration to obtain a to-be-superimposed signal; and
a logic controller, configured to superimpose the to-be-superimposed signal with the original PWM signal to generate a target PWM signal, wherein a pulse width of the target PWM signal is a sum of the pulse width of the original PWM signal and the preset delay duration;
wherein the preset delay duration is equal to an integer multiple of 1/N, which ranges from 1/N to N/N, of the period of the clock signal, and N is a preset positive integer.
2 . The system according to claim 1 , wherein:
the second voltage-controlled delayer and the logic controller are both components of a PWM circuit, the system comprises a plurality of PWM circuits, each PWM circuit of the plurality of PWM circuits is identical to the PWM circuit, and
PWM circuits of the plurality of PWM circuits are in one-to-one correspondence to respective current driving circuits of light emitting diodes (LEDs).
3 . The system according to claim 1 , wherein the phase-locked circuitry is a delay-locked loop (DLL).
4 . The system according to claim 1 , wherein the preset positive integer is 5.
5 . The system according to claim 1 , wherein the clock-signal generating circuitry is a clock generator.
6 . The system according to claim 1 , further comprising:
a memory configured to store the clock signal and the preset delay duration;
wherein the pulse generating circuitry is configured to generate the original PWM signal according to the stored clock signal and transmit the stored preset delay duration to the second voltage-controlled delayer.
7 . The system according to claim 6 , wherein the memory is a random-access memory (RAM).
8 . A light emitting diode (LED) display, comprising a system for pulse width modulation, wherein the system comprises:
clock-signal generating circuitry, configured to generate a clock signal;
pulse generating circuitry, configured to generate an original pulse width modulation (PWM) signal, of which a pulse width is a preset integer multiple of a period of the clock signal;
phase-locked circuitry, configured to generate a control voltage according to the clock signal;
a second voltage-controlled delayer, identical to a first voltage-controlled delayer in the phase-locked circuitry in structure, wherein the second voltage-controlled delayer is configured to delay, under excitation of the control voltage that is outputted by a filter in the phase-locked circuitry, the original PWM signal in phase by preset delay duration to obtain a to-be-superimposed signal; and
a logic controller, configured to superimpose the to-be-superimposed signal with the original PWM signal to generate a target PWM signal, wherein a pulse width of the target PWM signal is a sum of the pulse width of the original PWM signal and the preset delay duration;
wherein the preset delay duration is equal to an integer multiple of 1/N, which ranges from 1/N to N/N, of the period of the clock signal, and N is a preset positive integer.
9 . The LED display according to claim 8 , wherein:
the second voltage-controlled delayer and the logic controller are both components of a PWM circuit, the system comprises a plurality of PWM circuits, and each PWM circuit of the plurality of PWM circuits is identical to the PWM circuit, and
PWM circuits of the plurality of PWM circuits are in one-to-one correspondence to respective current driving circuits of light emitting diodes (LEDs).
10 . The LED display according to claim 8 , wherein the phase-locked circuitry is a delay-locked loop (DLL).
11 . The LED display according to claim 8 , wherein the preset positive integer is 5.
12 . The LED display according to claim 8 , wherein the clock-signal generating circuitry is a clock generator.
13 . The LED display according to claim 8 , further comprising:
a memory configured to store the clock signal and the preset delay duration;
wherein the pulse generating circuitry is configured to generate the original PWM signal according to the stored clock signal and transmit the stored preset delay duration to the second voltage-controlled delayer.
14 . The LED display according to claim 13 , wherein the memory is a random-access memory (RAM).