Memory with bitcell-to-periphery interface tap cell
A memory includes a periphery separated from one or more banks by a bitcell-to-periphery interface. The periphery includes logic circuits for the reading and writing to bitcells within the neighboring banks. Tap cells for the biasing of the periphery extend across the bitcell-to-periphery interface.
1 . A memory integrated onto a substrate, the substrate being doped according to a first conductivity type, the memory comprising:
a first bank of bitcells;
a periphery for the first bank of bitcells;
a first bitcell-to-periphery interface having a first boundary shared with the first bank of bitcells and having a second boundary shared with the periphery, wherein the substrate includes a first well doped according to a second conductivity type that extends across the periphery; and
a first tap cell doped according to the second conductivity type for biasing the first well, the first tap cell being located in a portion of the first well within the first bitcell-to-periphery interface,
wherein the first conductivity type is p-type and the second conductivity type is n-type, the first well being a first n-well and the first tap cell being a first n-doped tap cell,
wherein the first n-well has a height of two standard cells, and
wherein the first n-doped tap cell has a height of a single standard cell.
2 . The memory of claim 1 , further comprising:
a second n-well extending into the periphery, wherein the second n-well has a height of two standard cells and is spaced apart from the first n-well by a first substrate region of the periphery having a height of two standard cells; and
a second n-doped tap cell for biasing the second n-well, the second n-doped tap cell being located in a portion of the first bitcell-to-periphery interface containing the second n-well.
3 . The memory of claim 2 , wherein the second n-well extends across the periphery.
4 . The memory of claim 2 , wherein the second n-well extends from the first bitcell-to-periphery interface to an n-well-to-n-well gap in the periphery, the memory further comprising:
a second bank of bitcells;
a second bitcell-to-periphery interface, the second bitcell-to-periphery interface being positioned between the periphery and the second bank of bitcells;
a third n-well that extends from the n-well-to-n-well gap across the periphery towards the second bitcell-to-periphery interface; and
a third n-doped tap cell for biasing the third n-well, the third n-doped tap cell being located in a portion of the second bitcell-to-periphery interface containing the third n-well.
5 . The memory of claim 4 , wherein the third n-well has a height of two standard cells and the third n-doped tap cell has a height of a single standard cell.
6 . The memory of claim 3 , further comprising:
a second bank of bitcells;
a second bitcell-to-periphery interface, the second bitcell-to-periphery interface being positioned between the periphery and the second bank of bitcells; and
a plurality of p-doped tap cells for biasing p-doped substrate portions of the periphery, wherein the plurality of p-doped tap cells is arranged in a column across the second bitcell-to-periphery interface.
7 . The memory of claim 6 , wherein the first bitcell-to-periphery interface includes a column of n-doped tap cells.
8 . The memory of claim 2 , further comprising:
a first p-doped tap cell for biasing the first substrate region of the periphery, the first p-doped tap cell positioned in a portion of the first bitcell-to-periphery interface between the first n-well and the second n-well.
9 . The memory of claim 8 , wherein the first p-doped tap cell is separated from the first n-doped tap cell by a height of one standard cell and is separated from the second n-doped tap cell by a height of one standard cell, and wherein the memory is included within a cellular telephone.
10 . A method of biasing a periphery of a memory, comprising:
biasing a first n-well portion of the periphery from a first n-doped tap cell in a first interface between the periphery and a first bank of bitcells;
biasing a first p-doped substrate portion of the periphery from a first p-doped tap cell in the first interface; and
biasing a second n-well portion of the periphery from a second n-doped tap cell in the first interface, wherein the first p-doped substrate portion of the periphery separates the first n-well portion from the second n-well portion.
11 . A memory, comprising:
a first bank of bitcells;
a second bank of bitcells;
a periphery for the first bank of bitcells and for the second bank of bitcells;
a first interface between the first bank of bitcells and the periphery;
a second interface between the second bank of bitcells and the periphery; and
a plurality of n-doped tap cells for biasing n-well portion of the periphery, the plurality of n-doped tap cells being located within at least one of the first interface and the second interface.
12 . The memory of claim 11 , wherein each n-doped tap cell in the plurality of n-doped tap cells is located only within the first interface.
13 . The memory of claim 11 , wherein the plurality of n-doped tap cells is distributed across both the first interface and the second interface.
14 . The memory of claim 12 , further comprising:
a plurality of p-doped tap cells for biasing p-doped substrate portions of the periphery, wherein each p-doped tap cell in the plurality of p-doped tap cells is located only within the second interface.
15 . The memory of claim 13 , further comprising:
a plurality of p-doped tap cells for biasing p-doped substrate portions of the periphery, wherein the plurality of p-doped tap cells is distributed across both the first interface and the second interface.
16 . The memory of claim 15 , wherein the p-doped tap cells in the first interface alternate with the n-doped tap cells in the first interface.
17 . The memory of claim 16 , wherein adjacent ones of the p-doped tap cells and the n-doped tap cells in the first interface are spaced apart by a single standard cell height.