IP Library Granted Patent US 12690184
Granted Patent B2
US 12690184 · App. 18/604,825 · Granted Jul 21, 2026

Memory device with container-shaped electrode and method for fabricating the same

Inventor: Yuan-Yuan Lin (New Taipei City, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H10B12/03
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12690184
App. No.
18/604,825
Granted
Jul 21, 2026
Kind
B2
Abstract

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

Claims (15)

1 . A method for fabricating a memory device, comprising:

forming a landing area on a substrate;

forming an energy-removable layer adjacent to the landing area;

sequentially forming a first support layer, a first material layer, a second material layer, a second support layer, a third material layer, and a third support layer over the landing area, wherein the first material layer is doped with an N-type dopant and the third material layer is doped with a P-type dopant;

forming a first recess to expose the landing area;

forming a bottom electrode within the first recess;

conformally forming a dielectric layer on the bottom electrode and on a top surface of the third support layer;

forming a plurality of dielectric portions on top corners of the first recess;

conformally forming a top conductive layer on the dielectric layer and covering the plurality of dielectric portions; and

forming a top electrode on the top conductive layer.

2 . The method for fabricating the memory device of claim 1 , wherein the first support layer, the second support layer, and the third support layer comprise silicon nitride.

3 . The method for fabricating the memory device of claim 2 , wherein the first material layer, the second material layer, and the third material layer comprise polysilicon.

4 . The method for fabricating the memory device of claim 2 , a dimension of the first recess at a level of the first material layer is greater than a dimension of the first recess at a level of the third material layer.

5 . The method for fabricating the memory device of claim 1 , further comprising performing a thermal treating process to turn the energy-removable layer into an air gap structure comprising an air gap enclosed by a liner.

6 . The method for fabricating the memory device of claim 5 , wherein the energy-removable layer comprises a thermal decomposable material, a photonic decomposable material, or an e-beam decomposable material.