Structure with frontside and backside DRAMs

Inventors: Min Gyu Sung (Latham, NY); Kangguo Cheng (Schenectady, NY); Ruilong Xie (Niskayuna, NY); Chanro Park (Clifton Park, NY); Julien Frougier (Albany, NY)

Assignee: International Business Machines Corporation

H10B12/37 H10B12/315 H10W20/20

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Quick Facts

Patent No.: US 12690186
App. No.: 18/060,821
Granted: Jul 21, 2026
Kind: B2

External Links

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Abstract

A semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (DRAM) is located on a frontside of a semiconductor substrate, and a backside DRAM is located on a backside of the semiconductor substrate. Peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside DRAM.

Claims (27)

1 . A semiconductor structure comprising:

a semiconductor substrate having a frontside and a backside;

a frontside dynamic random access memory (DRAM) comprising a plurality of frontside transistors and a plurality of frontside capacitors located on the frontside of the semiconductor substrate;

a backside DRAM comprising a plurality of backside transistors and a plurality of backside capacitors located on the backside of the semiconductor substrate; and

a plurality of peripheral transistors located on the frontside of the semiconductor substrate and at a same device level as the plurality of frontside transistors, wherein the plurality of peripheral transistors are electrically connected to both the frontside DRAM and the backside DRAM.

2 . The semiconductor structure of claim 1 , wherein the plurality of peripheral transistors are connected to the backside DRAM through the semiconductor substrate.

3 . The semiconductor structure of claim 1 , wherein each frontside capacitor of the plurality of frontside capacitors is a frontside stacked capacitor.

4 . The semiconductor structure of claim 3 , wherein each backside capacitor of the plurality of backside capacitors is a backside trench capacitor.

5 . The semiconductor structure of claim 4 , wherein the backside trench capacitor is located in a backside semiconductor device layer of the semiconductor substrate.

6 . The semiconductor structure of claim 5 , wherein a portion of the backside semiconductor device layer is doped and serves as a first electrode of the backside trench capacitor.

7 . The semiconductor structure of claim 3 , wherein each backside capacitor of the plurality of backside capacitors is a backside stacked capacitor.

8 . The semiconductor structure of claim 7 , wherein the backside stacked capacitor is embedded in a backside interlayer dielectric material layer.

9 . The semiconductor structure of claim 1 , further comprising:

a frontside bitline located between the plurality of frontside transistors and the plurality of frontside capacitors.

10 . The semiconductor structure of claim 9 , wherein the frontside bitline is electrically connected to one source/drain region of each of the frontside transistors of the plurality of frontside transistors by a frontside bitline-to-transistor contact structure, and each of the frontside capacitors of the plurality of frontside capacitors is electrically connected to another source/drain region of each of the frontside transistors of the plurality of frontside transistors by a frontside capacitor-to-transistor contact structure, the frontside capacitor-to-transistor contact structure passes through a portion of the frontside bitline.

11 . The semiconductor structure of claim 1 , further comprising:

a backside bitline located between the plurality of backside transistors and the plurality of backside capacitors.

12 . The semiconductor structure of claim 11 , wherein each of the backside capacitors of the plurality of backside capacitors is a stacked capacitor, and wherein the backside bitline is electrically connected to one source/drain region of each of the backside transistors of the plurality of frontside transistors by a backside bitline-to-transistor contact structure, and each of the stacked capacitors is electrically connected to another source/drain region of each of the backside transistors of the plurality of backside transistors by a backside capacitor-to-transistor contact structure, the backside capacitor-to-transistor contact structure passes through a portion of the backside bitline.

13 . The semiconductor structure of claim 1 , further comprising:

a backside bitline vertically spaced apart from both the plurality of backside transistors and the plurality of backside capacitors.

14 . The semiconductor structure of claim 13 , wherein each of the backside capacitors of the plurality of backside capacitors is a trench capacitor, and wherein the backside bitline is electrically connected to one source/drain region of each of the backside transistors of the plurality of backside transistors by a backside bitline-to-transistor contact structure, and each of the trench capacitors is in direct physical contact with another source/drain region of each of the backside transistors of the plurality of backside transistors.

15 . The semiconductor structure of claim 1 , wherein the plurality of frontside transistors and the plurality of peripheral transistors are located on a frontside semiconductor device layer of the semiconductor substrate, and the plurality of backside transistors are located on a backside semiconductor device layer of the semiconductor substrate.

16 . The semiconductor structure of claim 15 , wherein and the frontside semiconductor device layer and the backside semiconductor device layer are spaced apart by a dielectric material layer.

17 . The semiconductor structure of claim 1 , wherein a first set of the plurality of peripheral transistors provides logic devices for the backside DRAM, and a second set of the plurality of peripheral transistors provides logic devices for the frontside DRAM.

18 . The semiconductor structure of claim 17 , wherein the first set of the plurality of peripheral transistors are electrically connected to a backside metal line by at least a backside metal via.

19 . The semiconductor structure of claim 17 , wherein the second set of the plurality of peripheral transistors are electrically connected to a frontside metal line by a frontside metal via and a frontside bitline-to-transistor contact structure.

20 . The semiconductor structure of claim 1 , wherein the frontside DRAM and the backside DRAM are vertically stacked one atop the other and a spaced apart from each other by at least a dielectric material layer of the semiconductor substrate.