Memory device and manufacturing method thereof
A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a semiconductor substrate, bit line structures, isolation structures, a storage node contact structure, and first voids. The bit line structures, the isolation structures, and the storage node contact structure are disposed on the semiconductor substrate. Each bit line structure extends in a first direction, and the bit line structures are arranged in a second direction. The isolation structures are located between the bit line structures adjacent to one another. The storage node contact structure is located between two adjacent bit line structures and located between two adjacent isolation structures in the first direction. The storage node contact structure includes four corner portions. The first voids are disposed in the storage node contact structure, and the first voids are located in at least two of the four corner portions.
1 . A memory device, comprising:
a semiconductor substrate;
bit line structures disposed on the semiconductor substrate, wherein each of the bit line structures extends in a first direction, and the bit line structures are arranged in a second direction;
isolation structures disposed on the semiconductor substrate, wherein the isolation structures are located between the bit line structures adjacent to one another;
a storage node contact structure disposed on the semiconductor substrate and located between two of the bit line structures adjacent to each other, wherein the storage node contact structure is located between two of the isolation structures adjacent to each other in the first direction, and the storage node contact structure comprises four corner portions; and
first voids disposed in the storage node contact structure, wherein the first voids are located in at least two of the four corner portions respectively, the storage node contact structure comprises an electrically conductive material, and a contour of each of the first voids is partially defined by the electrically conductive material.
2 . The memory device according to claim 1 , wherein the first voids are located in the four corner portions respectively.
3 . The memory device according to claim 1 , wherein the first voids are separated from one another.
4 . The memory device according to claim 1 , further comprising:
a second void disposed in the storage node contact structure and separated from the first voids.
5 . The memory device according to claim 4 , wherein the second void is larger than each of the first voids.
6 . The memory device according to claim 1 , wherein each of the four corner portions is disposed and surrounded by one of the two adjacent isolation structures and one of the two adjacent bit line structures.
7 . The memory device according to claim 1 , wherein each of the four corner portions directly contacts one of the two adjacent isolation structures, and each of the first voids directly contacts one of the two adjacent isolation structures.
8 . The memory device according to claim 1 , further comprising:
a recess extending downwards from a top surface of the storage node contact structure and located in one of the four corner portions; and
a sidewall structure disposed on the storage node contact structure and partially located in the recess, wherein a bottom of the sidewall structure is lower than a top of the storage node contact structure.
9 . The memory device according to claim 8 , wherein a width of the recess is greater than a width of the sidewall structure.
10 . The memory device according to claim 8 , wherein the recess is filled with at least two materials.
11 . The memory device according to claim 8 , wherein lower surfaces of the sidewall structure are not located in the same level.
12 . A manufacturing method of a memory device, comprising:
forming bit line structures on a semiconductor substrate, wherein each of the bit line structures extends in a first direction, and the bit line structures are arranged in a second direction;
forming isolation structures on the semiconductor substrate, wherein the isolation structures are located between the bit line structures adjacent to one another; and
forming a storage node contact structure on the semiconductor substrate, wherein the storage node contact structure is located between two of the bit line structures adjacent to each other, and the storage node contact structure is located between two of the isolation structures adjacent to each other in the first direction, wherein first voids are formed in the storage node contact structure, the storage node contact structure comprises four corner portions, and the first voids are located in at least two of the four corner portions respectively,
wherein the storage node contact structure comprises an electrically conductive material, and a contour of each of the first voids is partially defined by the electrically conductive material.
13 . The manufacturing method of the memory device according to claim 12 , wherein a method of forming the storage node contact structure comprises:
performing an epitaxial growth process for forming an electrically conductive epitaxial material on the semiconductor substrate, wherein space surrounded by the bit line structures and the isolation structures is filled with the electrically conductive epitaxial material, and the first voids are formed in the epitaxial growth process; and
performing an etching back process to the electrically conductive epitaxial material for forming the storage node contact structure.
14 . The manufacturing method of the memory device according to claim 13 , wherein at least one of the first voids becomes a recess extending downwards from a top surface of the storage node contact structure after the etching back process.
15 . The manufacturing method of the memory device according to claim 14 , further comprising:
forming a sidewall structure on the storage node contact structure, wherein the sidewall structure is formed on sidewalls of the two adjacent isolation structures and sidewalls of the two adjacent bit line structures, the sidewall structure is partially located in the recess, lower surfaces of the sidewall structure are not located in the same level, and a bottom of the sidewall structure is lower than a top of the storage node contact structure.
16 . The manufacturing method of the memory device according to claim 15 , further comprising:
forming an electrically conductive structure on the storage node contact structure, wherein the recess is filled with a part of the sidewall structure and a part of the electrically conductive structure.
17 . The manufacturing method of the memory device according to claim 13 , wherein a second void is formed in the electrically conductive epitaxial material by the epitaxial growth process, the second void is located in the storage node contact structure after the etching back process, the second void is separated from the first voids, and the second void is larger than each of the first voids.
18 . The manufacturing method of the memory device according to claim 12 , wherein the first voids are located in the four corner portions respectively, and the first voids are separated from one another.
19 . The manufacturing method of the memory device according to claim 12 , wherein each of the four corner portions is disposed and surrounded by one of the two adjacent isolation structures and one of the two adjacent bit line structures.
20 . The manufacturing method of the memory device according to claim 12 , wherein each of the four corner portions directly contacts one of the two adjacent isolation structures, and each of the first voids directly contacts one of the two adjacent isolation structures.
21 . A memory device, comprising:
a semiconductor substrate;
bit line structures disposed on the semiconductor substrate, wherein each of the bit line structures extends in a first direction, and the bit line structures are arranged in a second direction;
isolation structures disposed on the semiconductor substrate, wherein the isolation structures are located between the bit line structures adjacent to one another;
a storage node contact structure disposed on the semiconductor substrate and located between two of the bit line structures adjacent to each other, wherein the storage node contact structure is located between two of the isolation structures adjacent to each other in the first direction, and the storage node contact structure comprises four corner portions; and
first voids disposed in the storage node contact structure, wherein the first voids are located in at least two of the four corner portions respectively, each of the four corner portions directly contacts one of the two adjacent isolation structures, and each of the first voids directly contacts one of the two adjacent isolation structures.
22 . The memory device according to claim 21 , wherein the first voids are located in the four corner portions respectively.
23 . The memory device according to claim 21 , wherein the first voids are separated from one another.
24 . The memory device according to claim 21 , further comprising:
a second void disposed in the storage node contact structure and separated from the first voids.
25 . The memory device according to claim 24 , wherein the second void is larger than each of the first voids.
26 . The memory device according to claim 21 , wherein each of the four corner portions is disposed and surrounded by one of the two adjacent isolation structures and one of the two adjacent bit line structures.
27 . The memory device according to claim 21 , further comprising:
a recess extending downwards from a top surface of the storage node contact structure and located in one of the four corner portions; and
a sidewall structure disposed on the storage node contact structure and partially located in the recess, wherein a bottom of the sidewall structure is lower than a top of the storage node contact structure.
28 . The memory device according to claim 27 , wherein a width of the recess is greater than a width of the sidewall structure.
29 . The memory device according to claim 27 , wherein the recess is filled with at least two materials.
30 . The memory device according to claim 27 , wherein lower surfaces of the sidewall structure are not located in the same level.