MIM memory cell with backside interconnect structures

1 . A memory device, comprising:

a plurality of one-time programmable (OTP) memory cells, each OTP memory cell comprising:

a transistor disposed on a first side of a substrate; and

a capacitor disposed on a second side of the substrate opposite to the first side, and electrically connected to the transistor,

wherein the capacitor comprises a first terminal including a first interconnect metal via that is electrically connected to a source/drain structure of the transistor, a second terminal formed vertically lower than the first terminal and including a first interconnect metal line that is electrically connected to a bit line, and an insulation layer vertically interposed therebetween.

2 . The memory device of claim 1 , wherein a width of the insulation layer is greater than a width of a bottom surface of the first terminal.

3 . The memory device of claim 1 , wherein a width of the insulation layer is less than a width of a top surface of the second terminal.

4 . The memory device of claim 1 , wherein a width of the insulation layer is identical to a width of a top surface of the second terminal.

5 . The memory device of claim 1 , wherein the first terminal is electrically connected to a back side of a metal contact of the source/drain structure of the transistor through at least a back side metal via (VB).

6 . The memory device of claim 1 , wherein the insulation layer of the capacitor of the OTP memory cell is configured to be irreversibly broken down.

7 . The memory device of claim 1 , wherein the insulation layer has one or more materials selected from a group consisting of titanium nitride (TiN), tantalum nitride (TaN), an alloy of Ti and TiN, an alloy of Ta and TaN, an alloy of aluminum (Al) and oxygen (O), and combinations thereof.

8 . A memory device, comprising:

a transistor disposed on a first side of a substrate;

a capacitor disposed on a second side of the substrate opposite to the first side, the capacitor comprising a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer vertically interposed therebetween, and electrically connected to the transistor; and

a plurality of interconnect structures disposed below the second side of the substrate,

wherein the first terminal of the capacitor is a first interconnect structure, of the plurality of interconnect structures, that includes a metal via electrically connected to a source/drain structure of the transistor, and the second terminal of the capacitor is a second interconnect structure, of the plurality of interconnect structures, that includes a metal line electrically connected to a bit line.

9 . The memory device of claim 1 , wherein the first terminal is a first one of a plurality of interconnect structures disposed on the second side of the substrate, and the second terminal is a second one of the plurality of interconnect structures.

10 . The memory device of claim 8 , wherein the transistor and the capacitor form a one-time programmable (OTP) memory cell.

11 . The memory device of claim 10 , wherein the insulation layer of the capacitor is configured to be irreversibly broken down.

12 . The memory device of claim 8 , wherein a width of the insulation layer is greater than a width of a bottom surface the first terminal and less than a width of a top surface of the second terminal.

13 . The memory device of claim 8 , wherein a width of the insulation layer is less than a width of a bottom surface the first terminal and greater than a width of a top surface of the second terminal.

14 . The memory device of claim 8 , wherein a width of the insulation layer is less than or equal to a width of a bottom surface the first terminal and a top surface of the second terminal.

15 . The memory device of claim 8 , wherein a width of the insulation layer is greater than a width of a bottom surface the first terminal and a width of a top surface of the second terminal.

16 . A memory device, comprising:

a transistor disposed on a first side of a substrate; and

a capacitor disposed on a second side of the substrate opposite to the first side, and comprising a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer vertically interposed therebetween,

wherein the first terminal includes a first interconnect metal via that is electrically connected to a source/drain terminal contact of a source/drain terminal of the transistor from a back side of the source/drain terminal contact, and the second terminal includes a first interconnect metal line that is electrically connected to a bit line on the second side of the substrate.

17 . The memory device of claim 16 , wherein the first terminal is electrically connected to a source/drain terminal contact of a source/drain terminal of the transistor from a back side of the source/drain terminal contact by at least one back side metal via (VB) passing through the substrate.

18 . The memory device of claim 16 , wherein the transistor and the capacitor form a one-time programmable (OTP) memory cell, and wherein the insulation layer of the capacitor is configured to be irreversibly broken down.

19 . The memory device of claim 16 , further comprising:

a plurality of interconnect structures disposed below the second side of the substrate, wherein the first terminal of the capacitor is a first interconnect structure of the plurality of interconnect structures, and the second terminal of the capacitor is a second interconnect structure of the plurality of interconnect structures.

20 . The memory device of claim 16 , wherein the insulation layer has one or more materials selected from a group consisting of titanium nitride (TiN), tantalum nitride (TaN), an alloy of Ti and TiN, an alloy of Ta and TaN, an alloy of aluminum (Al) and oxygen (O), and combinations thereof.